llvm-svn: 118446

llvm-svn: 118445

Major cleanup of whitespace and formatting issues in MBlaze backend

llvm-svn: 118434

llvm-svn: 118429

llvm-svn: 118422

llvm-svn: 118413

llvm-svn: 118398

llvm-svn: 118397

llvm-svn: 118396

an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390

llvm-svn: 118389

of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.

llvm-svn: 118378

llvm-svn: 118375

implementing rdar://8431864

llvm-svn: 118364

the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363

different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362

llvm-svn: 118361

to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360

llvm-svn: 118358

- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357

exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356

shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355

listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354

llvm-svn: 118353

fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352

(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351

add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350

llvm-svn: 118349

llvm-svn: 118348

llvm-svn: 118347

floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346

llvm-svn: 118341

llvm-svn: 118340

llvm-svn: 118339

while the latter doesn't.

llvm-svn: 118338

llvm-svn: 118337

result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334

Fixes 8559.

llvm-svn: 118333

llvm-svn: 118332

tidy up the movsx and movzx aliases.

llvm-svn: 118331