so that it can be reused in MemCpyOptimizer.  This analysis is needed to remove
an unnecessary memcpy when returning a struct into a local variable.
rdar://11341081
PR12686

llvm-svn: 156776

llvm-svn: 156775

llvm-svn: 156774

llvm-svn: 156772

llvm-svn: 156770

Returning a temporary BitVector is very expensive. If you must, create
the temporary explicitly: Use BitVector(A).flip() instead of ~A.

llvm-svn: 156768

These operators were crazy slow, calling malloc to return a temporary
result. At the same time, they look very innocent when used in code.

If you need temporary BitVectors to compute your thing, create them
explicitly, and use the inplace logical operators. This makes the high
cost explicit in the code.

llvm-svn: 156767

Register units can be used to compute if two registers overlap:

  A overlaps B iff units(A) intersects units(B).

With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.

When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.

With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.

llvm-svn: 156763

The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.

Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().

llvm-svn: 156762

TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.

This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.

TopoSigs are not currently exposed outside TableGen.

llvm-svn: 156761

The existing operation (A & B).any() is very slow.

llvm-svn: 156760

llvm-svn: 156757

llvm-svn: 156756

llvm-svn: 156755

llvm-svn: 156754

llvm-svn: 156745

Found by valgrind.

llvm-svn: 156744

llvm-svn: 156743

ReleaseNotes: Add a note about zero_undef on llvm.cttz/ctlz. Extend x86 section. Add a bullet for dwarf access tables.

llvm-svn: 156740

ReleaseNotes: Add a blurb about llvm-mc -g and move inliner changes into the optimizer sections. Verbosify some bullets.

llvm-svn: 156739

                            ^~~~
                            llvm-build

llvm-svn: 156738

llvm-svn: 156737

llvm-svn: 156736

llvm-svn: 156735

llvm-svn: 156733

llvm-svn: 156732

llvm-svn: 156731

llvm-svn: 156730

llvm-svn: 156729

llvm-svn: 156724

llvm-svn: 156716

for nesting.

llvm-svn: 156714

llvm-svn: 156712

Based on a patch by Team PaX.

llvm-svn: 156709

Patch by Team PaX!

llvm-svn: 156708

llvm-svn: 156707

Based on a patch from PaX Team.

llvm-svn: 156706

Based on a patch from PaX Team.

llvm-svn: 156705

Ordinary patch for PR1255.
Added new case-ranges orientated methods for adding/removing cases in SwitchInst. After this patch cases will internally representated as ConstantArray-s instead of ConstantInt, externally cases wrapped within the ConstantRangesSet object.
Old methods of SwitchInst are also works well, but marked as deprecated. So on this stage we have no side effects except that I added support for case ranges in BitcodeReader/Writer, of course test for Bitcode is also added. Old "switch" format is also supported.

llvm-svn: 156704

the address of a function.

llvm-svn: 156703