size of the clang binary in Debug builds from 690MB to 679MB.

llvm-svn: 129518

llvm-svn: 129517

improvements, that will lead to fixing PR6627.

llvm-svn: 129504

(movzx/movsx) because they give more information. Revert that part of the patch.

llvm-svn: 129498

cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497

the alias".

llvm-svn: 129485

rdar://problem/9280370

llvm-svn: 129480

Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).

rdar://problem/9280470

llvm-svn: 129471

rdar://problem/9279440

llvm-svn: 129469

llvm-svn: 129468

ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.

llvm-svn: 129466

rdar://problem/9276651

llvm-svn: 129462

rdar://problem/9276427

llvm-svn: 129456

llvm-svn: 129451

the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.

llvm-svn: 129432

llvm-svn: 129429

alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.

llvm-svn: 129428

llvm-svn: 129419

rdar://problem/9273947

llvm-svn: 129411

The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409

llvm-svn: 129403

Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.

llvm-svn: 129401

In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391

rdar://problem/9269047

llvm-svn: 129387

be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377

llvm-svn: 129365

stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345

Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325

rdar://problem/9267838

llvm-svn: 129320

llvm-svn: 129313

llvm-svn: 129311

This fixes http://llvm.org/bugs/show_bug.cgi?id=9653

llvm-svn: 129303

Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.

rdar://problem/9266265

llvm-svn: 129298

Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.

llvm-svn: 129294

llvm-svn: 129288

invalid instructions.

llvm-svn: 129286

disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284

llvm-svn: 129271

llvm-svn: 129248

InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.

llvm-svn: 129223