a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

llvm-svn: 9903

Header files will be on the way.

llvm-svn: 9298

llvm-svn: 8588

llvm-svn: 7675

llvm-svn: 7617

so get rid of the def/use parameters that were getting passed in.

**** This now changes the semantics of these methods to preserve the flags,
     not clobber them!

llvm-svn: 7602

llvm-svn: 7534

llvm-svn: 7531

which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

llvm-svn: 6468

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 5301

llvm-svn: 5272

llvm-svn: 5217

llvm-svn: 5194

llvm-svn: 5053

llvm-svn: 4737

llvm-svn: 4719

llvm-svn: 4447

llvm-svn: 4446

llvm-svn: 4438

llvm-svn: 4435

llvm-svn: 4426

instead record them as extra operands in the operands[] vector.
Also, move CallArgsDescriptor into this class instead of making it an
annotation on the machine instruction.

llvm-svn: 4399

MachineInstr.cpp

llvm-svn: 4392

llvm-svn: 4389

llvm-svn: 4359

llvm-svn: 4358

llvm-svn: 4357

  by MachineInstr.
* Add a bunch of new methods to allow incremental addition of operands to the
  machine instr instance.

llvm-svn: 4356

llvm-svn: 4348

  - Inline methods that are mostly a single line anyway
  - Eliminate several methods that were never called
  - Group methods a bit more consistently

llvm-svn: 4329

llvm-svn: 4327

    overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
    bitvector.  Sped up LLC a little less than 10% in a debug build!

llvm-svn: 4261

llvm-svn: 3843

llvm-svn: 3737

one Value with another one in all operands and implicit references
of the machine instruction.

llvm-svn: 3306

* Removed extraneous #includes
* Fixed file headers to be consistent with the rest of LLVM
* Other minor fixes

llvm-svn: 3278

llvm-svn: 3075