llvm-svn: 54411

Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.

llvm-svn: 54403

llvm-svn: 54376

llvm-svn: 54350

llvm-svn: 54336

- Add a basic machine-level dead block eliminator.

These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.

llvm-svn: 54333

llvm-svn: 54329

aren't used anyway, they also used to broke compiling when fastcc was specified for a
function, but not anymore.

llvm-svn: 54316

llvm-svn: 54315

llvm-svn: 54314

llvm-svn: 54313

llvm-svn: 54312

Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug

llvm-svn: 54274

llvm-svn: 54273

llvm-svn: 54250

the default legalizer.

llvm-svn: 54249

switches use the binary search algorithm) for
environments that don't support it.  PPC64 JIT
is such an environment; turn the flag on for that.

llvm-svn: 54248

access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

llvm-svn: 54229

subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.

llvm-svn: 54223

llvm-svn: 54215

llvm-svn: 54214

llvm-svn: 54213

llvm-svn: 54212

llvm-svn: 54169

llvm-svn: 54168

llvm-svn: 54167

llvm-svn: 54148

which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

llvm-svn: 54147

llvm-svn: 54142

of operands should be -1 not 0.

llvm-svn: 54141

Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.

llvm-svn: 54139

llvm-svn: 54131

llvm-svn: 54128

parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.

llvm-svn: 54127

mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch

llvm-svn: 54039

llvm-svn: 54029

llvm-svn: 54026

llvm-svn: 54004

large numbers of CBE regressions caused by r53958.

llvm-svn: 53990

Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.

llvm-svn: 53979