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  1. Feb 19, 2011
    • Chris Lattner's avatar
      Implement rdar://9009151, transforming strided loop stores of · 0f4a6401
      Chris Lattner authored
      unsplatable values into memset_pattern16 when it is available
      (recent darwins).  This transforms lots of strided loop stores
      of ints for example, like 5 in vpr:
      
        Formed memset:   call void @memset_pattern16(i8* %4, i8* getelementptr inbounds ([16 x i8]* @.memset_pattern9, i32 0, i32 0), i64 %tmp25)
          from store to: {%3,+,4}<%11> at:   store i32 3, i32* %scevgep, align 4, !tbaa !4
      
      llvm-svn: 126040
      0f4a6401
  2. Feb 18, 2011
  3. Feb 17, 2011
  4. Feb 15, 2011
  5. Feb 14, 2011
  6. Feb 13, 2011
  7. Feb 12, 2011
  8. Feb 11, 2011
  9. Feb 10, 2011
    • Chris Lattner's avatar
      implement the first part of PR8882: when lowering an inbounds · d86ded17
      Chris Lattner authored
      gep to explicit addressing, we know that none of the intermediate
      computation overflows.
      
      This could use review: it seems that the shifts certainly wouldn't
      overflow, but could the intermediate adds overflow if there is a 
      negative index?
      
      Previously the testcase would instcombine to:
      
      define i1 @test(i64 %i) {
        %p1.idx.mask = and i64 %i, 4611686018427387903
        %cmp = icmp eq i64 %p1.idx.mask, 1000
        ret i1 %cmp
      }
      
      now we get:
      
      define i1 @test(i64 %i) {
        %cmp = icmp eq i64 %i, 1000
        ret i1 %cmp
      }
      
      llvm-svn: 125271
      d86ded17
    • Chris Lattner's avatar
      Enhance a bunch of transformations in instcombine to start generating · 6b657aed
      Chris Lattner authored
      exact/nsw/nuw shifts and have instcombine infer them when it can prove
      that the relevant properties are true for a given shift without them.
      
      Also, a variety of refactoring to use the new patternmatch logic thrown
      in for good luck.  I believe that this takes care of a bunch of related
      code quality issues attached to PR8862.
      
      llvm-svn: 125267
      6b657aed
    • Chris Lattner's avatar
      Enhance the "compare with shift" and "compare with div" · 98457101
      Chris Lattner authored
      optimizations to be much more aggressive in the face of
      exact/nsw/nuw div and shifts.  For example, these (which
      are the same except the first is 'exact' sdiv:
      
      define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
        %A = sdiv exact i64 %X, -5   ; X/-5 == 0 --> x == 0
        %B = icmp eq i64 %A, 0
        ret i1 %B
      }
      
      define i1 @sdiv_icmp4(i64 %X) nounwind {
        %A = sdiv i64 %X, -5   ; X/-5 == 0 --> x == 0
        %B = icmp eq i64 %A, 0
        ret i1 %B
      }
      
      compile down to:
      
      define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
        %1 = icmp eq i64 %X, 0
        ret i1 %1
      }
      
      define i1 @sdiv_icmp4(i64 %X) nounwind {
        %X.off = add i64 %X, 4
        %1 = icmp ult i64 %X.off, 9
        ret i1 %1
      }
      
      This happens when you do something like:
        (ptr1-ptr2) == 42
      
      where the pointers are pointers to non-unit types.
      
      llvm-svn: 125266
      98457101
    • Chris Lattner's avatar
      more cleanups, notably bitcast isn't used for "signed to unsigned type · dcef03fb
      Chris Lattner authored
      conversions". :)
      
      llvm-svn: 125265
      dcef03fb
    • Chris Lattner's avatar
      A bunch of cleanups and simplifications using the new PatternMatch predicates · 7d0e43ff
      Chris Lattner authored
      and generally tidying things up.  Only very trivial functionality changes
      like now doing (-1 - A) -> (~A) for vectors too.
      
       InstCombineAddSub.cpp |  296 +++++++++++++++++++++-----------------------------
       1 file changed, 126 insertions(+), 170 deletions(-)
      
      llvm-svn: 125264
      7d0e43ff
    • Chris Lattner's avatar
      teach SimplifyDemandedBits that exact shifts demand the bits they · 768003c5
      Chris Lattner authored
      are shifting out since they do require them to be zeros.  Similarly
      for NUW/NSW bits of shl
      
      llvm-svn: 125263
      768003c5
    • Eric Christopher's avatar
      Revert this in an attempt to bring the builders back. · da6bd450
      Eric Christopher authored
      llvm-svn: 125257
      da6bd450
    • Cameron Zwarich's avatar
      Turn this pass ordering: · 58c8670a
      Cameron Zwarich authored
      Natural Loop Information
       Loop Pass Manager
         Canonicalize natural loops
       Scalar Evolution Analysis
       Loop Pass Manager
         Induction Variable Users
         Canonicalize natural loops
         Induction Variable Users
         Loop Strength Reduction
      
      into this:
      
      Scalar Evolution Analysis
      Loop Pass Manager
        Canonicalize natural loops
        Induction Variable Users
        Loop Strength Reduction
      
      This fixes <rdar://problem/8869639>. I also filed PR9184 on doing this sort of
      thing automatically, but it seems easier to just change the ordering of the
      passes if this is the only case.
      
      llvm-svn: 125254
      58c8670a
  10. Feb 09, 2011
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