llvm-svn: 190259

llvm-svn: 190258

precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235

llvm-svn: 190234

functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.

llvm-svn: 190233

llvm-svn: 190232

a DISubprogram.
    
Verifier is updated accordingly.

llvm-svn: 190229

into a 5-bit or 6-bit field.

llvm-svn: 190226

Remove one cast and improve readability. No functionality change.

llvm-svn: 190225

llvm-svn: 190224

llvm-svn: 190221

equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220

llvm-svn: 190219

instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200

a DICompositeType.
    
Verifier is updated accordingly.

llvm-svn: 190190

of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.

llvm-svn: 190188

llvm-svn: 190181

llvm-svn: 190180

llvm-svn: 190179

llvm-svn: 190178

The latency based scheduling could induce spills in some cases.

llvm-svn: 190177

Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176

llvm-svn: 190170

llvm-svn: 190169

The if above it ensures the property anyway.

llvm-svn: 190168

There's no 'B3' in the example.

llvm-svn: 190167

llvm-svn: 190156

Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155

This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.

llvm-svn: 190154

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153

This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.

llvm-svn: 190152

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150

This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.

llvm-svn: 190148

Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145

llvm-svn: 190144

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143