llvm-svn: 140352

worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349

We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348

llvm-svn: 140347

Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
These are very much a work in progress, and not really useful yet.

llvm-svn: 140345

Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340

The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339

floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332

llvm-svn: 140327

llvm-svn: 140325

llvm-svn: 140324

a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319

llvm-svn: 140318

VK_Mips_GPOFF_LO.

llvm-svn: 140316

llvm-svn: 140315

llvm-svn: 140313

llvm-svn: 140310

to fix up parameter passing on SM < 2.0

llvm-svn: 140309

llvm-svn: 140308

llvm-svn: 140307

llvm-svn: 140306

instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305

Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960

llvm-svn: 140299

llvm-svn: 140297

- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296

llvm-svn: 140295

llvm-svn: 140294

llvm-svn: 140292

llvm-svn: 140291

Turns out that Thumb2 ADR doesn't need special printing like LDR does.  Fix other test failures I caused.

llvm-svn: 140284

Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283

Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.

llvm-svn: 140282

llvm-svn: 140281

This makes sure that the unwind destination of an invoke is a landing pad.

llvm-svn: 140280

This inserts a cleanup landingpad instruction and a resume to mimic the old
unwind instruction.

llvm-svn: 140277

Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

llvm-svn: 140276

llvm-svn: 140275

patch contributed by Jia Liu!

llvm-svn: 140273

These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.

llvm-svn: 140267

MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261