We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348

floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332

llvm-svn: 140325

llvm-svn: 140324

a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319

VK_Mips_GPOFF_LO.

llvm-svn: 140316

llvm-svn: 140315

llvm-svn: 140313

llvm-svn: 140310

to fix up parameter passing on SM < 2.0

llvm-svn: 140309

llvm-svn: 140308

llvm-svn: 140307

llvm-svn: 140306

instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305

Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960

llvm-svn: 140299

llvm-svn: 140297

- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296

llvm-svn: 140295

llvm-svn: 140294

llvm-svn: 140292

llvm-svn: 140291

Turns out that Thumb2 ADR doesn't need special printing like LDR does.  Fix other test failures I caused.

llvm-svn: 140284

Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283

Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

llvm-svn: 140276

patch contributed by Jia Liu!

llvm-svn: 140273

These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.

llvm-svn: 140267

MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261

llvm-svn: 140258

should be initialized to UnknownABI.

llvm-svn: 140254

Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.

llvm-svn: 140246

  assert(!"error message");

To:

  assert(0 && "error message");

which is more consistant across the code base.

llvm-svn: 140234

llvm-svn: 140233

Check if architecture & ABI combination is valid.

llvm-svn: 140230

llvm-svn: 140229

This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228

llvm-svn: 140227

In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.

llvm-svn: 140217

llvm-svn: 140214

llvm-svn: 140203

llvm-svn: 140199