with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095

address register writeback.

llvm-svn: 99094

rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093

writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090

and use this (as well as getCalledValue) to access the callee,
instead of {g|s}etOperand(0).

llvm-svn: 99084

llvm-svn: 99083

address register writeback.

llvm-svn: 99082

llvm-svn: 99081

rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080

llvm-svn: 99078

load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066

writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065

llvm-svn: 99062

PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*.

llvm-svn: 99061

--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049

load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043

so that the SCEVExpander doesn't retain a dangling pointer as its
insert position. The dangling pointer in this case wasn't ever used
to insert new instructions, but it was causing trouble with
SCEVExpander's code for automatically advancing its insert position
past debug intrinsics.

This fixes use-after-free errors that valgrind noticed in
test/Transforms/IndVarSimplify/2007-06-06-DeleteDanglesPtr.ll and
test/Transforms/IndVarSimplify/exit_value_tests.ll.

llvm-svn: 99036

caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.

llvm-svn: 99032

llvm-svn: 99031

llvm-svn: 99014

IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

llvm-svn: 99013

--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010

use-before-def errors in SCEVExpander-produced code in sqlite3 when debug
info with optimization is enabled, though the testcases for this are
dependent on use-list order.

llvm-svn: 99001

that they are dead.

llvm-svn: 99000

llvm-svn: 98994

is valid, but not useful, when variable  identified by !1 is optimized away by the optimizer.

llvm-svn: 98986

override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980

disabled for several months (since svn r88806) and no one noticed.  My fix
for pr6543 yesterday reenabled it, but broke the ARM port's code for using
TBB/TBH.  Rather than adding a target hook to disable merging for Thumb2 only,
I'm just taking this out.  It is not common to have identical jump tables,
the code we used to merge them was O(N^2), and it only helps code size, not
performance.

llvm-svn: 98977

 - This is "extraordinarily" Darwin 'as' compatible. See the litany of FIXMEs littered about for more information.
 - There are a few cases which seem to clearly be 'as' bugs which I have left unsupported, and there is one cases where we diverge but should fix if it blocks diffing .o files (Darwin 'as' ends up widening a jump unnecessarily).
 - 403.gcc build, runs, and diffs equivalently to the 'as' built version now (using llvm-mc). However, it builds so slowly that I wouldn't recommend trying it quite yet. :)

llvm-svn: 98974

MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98972

room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

llvm-svn: 98967

back out r98957, it broke http://smooshlab.apple.com:8010/builders/clang-x86_64-darwin10-fnt/builds/703 in the nightly test suite

llvm-svn: 98958

This time I did a self-hosted bootstrap on Linux x86-64,
with no problems. Let's see how darwin 64-bit self-hosting
goes. At the first sign of failure I'll back this out.

Maybe the valgrind bots give me a hint of what may be wrong
(it at all).

llvm-svn: 98957

 - MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

llvm-svn: 98955

llvm-svn: 98954

llvm-svn: 98953

llvm-svn: 98952

llvm-svn: 98950

llvm-svn: 98949

llvm-svn: 98948