This makes the local register allocator about 20% faster.

llvm-svn: 101574

llvm-svn: 101573

to keep the node entries in scc_iterator up to date instead of dangling as
the SCC mutates.

This is a really terrible problem which was causing -g to affect codegen 
because it would permute the memory image of the compiler process.

Thanks to Dale for expertly hunting it down.

llvm-svn: 101565

llvm-svn: 101564

on it.

llvm-svn: 101563

No functionality change.

llvm-svn: 101562

to CallGraphSCCPass's instead of passing around a
std::vector<CallGraphNode*>.  No functionality change,
but now we have a much tidier interface.

llvm-svn: 101558

case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557

(i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test case until -promote-16bit is enabled.

llvm-svn: 101551

llvm-svn: 101543

llvm-svn: 101538

SelectionDAG-specific parts of TargetLowering.

llvm-svn: 101537

llvm-svn: 101532

llvm-svn: 101531

this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529

to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527

considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.

llvm-svn: 101524

llvm-svn: 101501

llvm-svn: 101500

llvm-svn: 101480

llvm-svn: 101478

llvm-svn: 101477

dependent analyses, and increase code size, so doing it profitably would
require more complex heuristics.

llvm-svn: 101471

callee is expected to be expanded to something else by codegen, so that
normal infinitely recursive calls are still transformed.

llvm-svn: 101468

with a fix for self-hosting

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101465

llvm-svn: 101463

expression canonicalization. Its job is to print what's there, not to
make judgements about it.

llvm-svn: 101461

JIT doesn't use the MC back-end asm printer to emit labels that it uses, the
section for the MCSymbol is never set. And thus the MCSymbol for the EH label
isn't marked as "defined". Because of that, TidyLandingPads removes the needed
landing pads from the JIT output. This breaks EH for every JIT program.

This is a work-around for this limitation. We pass in the label locations
map. If the label has a non-zero value, then it was "emitted" by the JIT and
TidyLandingPads shouldn't remove that label.

A nicer solution would be to mark the MCSymbol as "used" by the JIT and not rely
upon the section being set to determine if it's defined or not.

llvm-svn: 101453

Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.

llvm-svn: 101448

llvm-svn: 101446

llvm-svn: 101443

llvm-svn: 101438

llvm-svn: 101437

llvm-svn: 101434

wanted the alignment of the pointee.

llvm-svn: 101432

llvm-svn: 101429

place.

llvm-svn: 101427

ConvertToScalarInfo.

llvm-svn: 101425

llvm-svn: 101423

CanConvertToScalar/MergeInType.  Eliminate a pointless
LLVMContext argument to MergeInType.

llvm-svn: 101422