- Jun 25, 2013
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Manman Ren authored
llvm-svn: 184866
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Bill Wendling authored
llvm-svn: 184864
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Ulrich Weigand authored
[PowerPC] Support @got modifier Add VK_... values and relocation types necessary to support the @got family of modifiers. Used by the asm parser only. llvm-svn: 184860
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Rafael Espindola authored
llvm-svn: 184853
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Rafael Espindola authored
llvm-svn: 184852
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Aaron Watry authored
By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184848
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Aaron Watry authored
Add test cases for both vector sizes on SI and also add v2i32 test for EG. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184846
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UREM produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184844
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UDIV produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184843
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184842
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184841
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184840
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184839
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184838
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Aaron Watry authored
Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184837
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Benjamin Kramer authored
This is a band-aid to fix the most severe regressions we're seeing from basing spill decisions on block frequencies, until we have a better solution. llvm-svn: 184835
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Ulrich Weigand authored
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
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Ulrich Weigand authored
[PowerPC] Add rldcr/rldic instructions This adds pattern for the rldcr and rldic instructions (the last instruction from the rotate/shift family that were missing). They are currently used only by the asm parser. llvm-svn: 184833
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Ulrich Weigand authored
[PowerPC] Add extended subtract mnemonics This adds support for the extended subtract mnemonics to the asm parser: subi subis subic subic. sub sub. subc subc. llvm-svn: 184832
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Justin Holewinski authored
llvm-svn: 184831
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Nadav Rotem authored
llvm-svn: 184827
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Rafael Espindola authored
llvm-svn: 184826
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Rafael Espindola authored
llvm-svn: 184824
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Andrew Trick authored
This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
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Tom Stellard authored
In reality, some unaligned memory accesses are legal for 32-bit types and smaller too, but it all depends on the address space. Allowing unaligned loads/stores for > 32-bit types is mainly to prevent the legalizer from splitting one load into multiple loads of smaller types. https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 184822
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Tom Stellard authored
Tested-By:
Aaron Watry <awatry@gmail.com> llvm-svn: 184821
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Tom Stellard authored
Tested-By:
Aaron Watry <awatry@gmail.com> llvm-svn: 184820
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Tom Stellard authored
This should only make a difference in programs that use a lot of the vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight improvement in the phatk bitcoin mining kernel with this patch on Evergreen (vector size == 1): Before: 1173 Instruction Groups / 9520 dwords After: 1167 Instruction Groups / 9510 dwords Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184819
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NAKAMURA Takumi authored
llvm-svn: 184809
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Rafael Espindola authored
This is really ugly, but it is no worse than what we have in clang right now and it is better to get it working first and clean/optimize it afterwards. Will be tested from clang in the next patch. llvm-svn: 184802
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Eric Christopher authored
llvm-svn: 184792
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- Jun 24, 2013
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Eric Christopher authored
llvm-svn: 184788
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Adrian Prantl authored
llvm-svn: 184783
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Eric Christopher authored
never modified. No functional change. llvm-svn: 184781
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Ulrich Weigand authored
[PowerPC] Support some miscellaneous mnemonics in the asm parser This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
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David Blaikie authored
Representing enumerators by int64 instead of uint64 for now. At some point we need to address the underlying issue of representation depending on the specific enumeration. llvm-svn: 184761
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Benjamin Kramer authored
llvm-svn: 184758
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Aaron Watry authored
our -> or llvm-svn: 184756
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Ulrich Weigand authored
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
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Nadav Rotem authored
llvm-svn: 184749
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