into a roundss intrinsic, producing a cyclic dag.  The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection.  Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.

llvm-svn: 96408

with chains.  On interior nodes that lead up to them, we just directly
check that there is a single use.  This generates slightly more
efficient code.

llvm-svn: 96366

llvm-svn: 96337

llvm-svn: 96333

llvm-svn: 96332

(isprofitable|islegal)tofold checks.

llvm-svn: 96331

IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255

produce a table based matcher instead of gobs of C++ Code.

Though it's not done yet, the shrinkage seems promising,
the table for the X86 ISel is 75K and still has a lot of 
optimization to come (compare to the ~1.5M of .o generated
the old way, much of which will go away).

The code is currently disabled by default (the #if 0 in
DAGISelEmitter.cpp).  When enabled it generates a dead
SelectCode2 function in the DAGISel Header which will
eventually replace SelectCode.

There is still a lot of stuff left to do, which are
documented with a trail of FIXMEs.

llvm-svn: 96215

on TreePatternNode to be methods on TreePatternNode.

llvm-svn: 96197

that predated -fast-isel which attempted to speed up the dag pattern
matchers at -O0.  Since fast-isel is around, this is basically 
obsolete and removing it shrinks the generated dag isels.

llvm-svn: 96188

class out of line.

llvm-svn: 96113

clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564

verifying that the special case does not occur.

llvm-svn: 92504

for a refactoring I'm working on.

llvm-svn: 92503

llvm-svn: 91741

Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711

forward declaration and patching tblgen to emit it right. Patch by Amine Khaldi!

llvm-svn: 88798

since the instruction might use the other result of different type.

llvm-svn: 86462

llvm-svn: 85556

*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.

llvm-svn: 85530

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

llvm-svn: 84193

 - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790

Partial fix for PR4946.

llvm-svn: 81518

update all code that this affects.

llvm-svn: 79830

llvm-svn: 79821

llvm-svn: 79742

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610

llvm-svn: 78417

llvm-svn: 77613

llvm-svn: 77503

Also remove trailing semicolon.

llvm-svn: 75027

 - Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742

llvm-svn: 72712

ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.

llvm-svn: 72707

Should remove a warning from MSVC.

llvm-svn: 71603

llvm-svn: 70879

which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440