- Aug 08, 2007
-
-
Evan Cheng authored
llvm-svn: 40925
-
Evan Cheng authored
- Fix some minor bugs related to special markers on val# def. ~0U means undefined, ~1U means dead val#. llvm-svn: 40916
-
Evan Cheng authored
kill instruction #, and source register number (iff the value# is defined by a copy). - Now def instruction # is set for every value#, not just for copy defined ones. - Update some outdated code related inactive live ranges. - Kill info not yet set. That's next patch. llvm-svn: 40913
-
- Jun 27, 2007
-
-
Evan Cheng authored
llvm-svn: 37764
-
Evan Cheng authored
llvm-svn: 37743
-
- Jun 19, 2007
-
-
Dan Gohman authored
with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
-
- Jun 14, 2007
-
-
Dan Gohman authored
implementation for x86. llvm-svn: 37576
-
- Jun 08, 2007
-
-
David Greene authored
simultaneously. Move that pass to SimpleRegisterCoalescing. This makes it easier to implement alternative register allocation and coalescing strategies while maintaining reuse of the existing live interval analysis. llvm-svn: 37520
-
- May 14, 2007
-
-
Evan Cheng authored
llvm-svn: 37052
-
Evan Cheng authored
v1 = r2 = move v1 = op r2<kill> ... r2 = move v1 = op r2<kill> Clear the first r2 kill if v1 and r2 are joined. llvm-svn: 37050
-
- May 03, 2007
-
-
Devang Patel authored
llvm-svn: 36662
-
- May 02, 2007
-
-
Devang Patel authored
Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. llvm-svn: 36652
-
Lauro Ramos Venancio authored
llvm-svn: 36648
-
- May 01, 2007
-
-
Devang Patel authored
llvm-svn: 36632
-
- Apr 26, 2007
-
-
Evan Cheng authored
llvm-svn: 36483
-
- Apr 25, 2007
-
-
Evan Cheng authored
- A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. llvm-svn: 36434
-
- Apr 18, 2007
-
-
Evan Cheng authored
llvm-svn: 36250
-
Evan Cheng authored
llvm-svn: 36240
-
- Apr 17, 2007
-
-
Evan Cheng authored
long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. llvm-svn: 36218
-
- Apr 04, 2007
-
-
Evan Cheng authored
llvm-svn: 35660
-
Evan Cheng authored
Trivially re-materializable instructions have spill weights that are half of what it would be otherwise. llvm-svn: 35658
-
- Apr 02, 2007
-
-
Evan Cheng authored
llvm-svn: 35600
-
- Mar 30, 2007
-
-
Evan Cheng authored
of dead def live interval at 1 to avoid multiple def's targeting the same register. The previous patch missed a case where the source operand is live-in. In that case, remove the whole interval. llvm-svn: 35512
-
- Mar 28, 2007
-
-
Evan Cheng authored
llvm-svn: 35419
-
Evan Cheng authored
not violate that. llvm-svn: 35396
-
- Mar 27, 2007
-
-
Evan Cheng authored
llvm-svn: 35365
-
- Mar 22, 2007
-
-
Evan Cheng authored
where the destination is dead. llvm-svn: 35252
-
- Mar 20, 2007
-
-
Evan Cheng authored
llvm-svn: 35208
-
- Mar 19, 2007
-
-
Evan Cheng authored
llvm-svn: 35165
-
Evan Cheng authored
llvm-svn: 35153
-
- Mar 18, 2007
-
-
Evan Cheng authored
- Use distance to closest use to determine whether to abort coalescing. llvm-svn: 35141
-
- Mar 17, 2007
-
-
Evan Cheng authored
to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
-
- Mar 15, 2007
-
-
Evan Cheng authored
llvm-svn: 35117
-
- Mar 03, 2007
-
-
Evan Cheng authored
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0): Live Ins: %r0 %r1 %r2 %r3 %reg1032 = tMOVrr %r3<kill> %reg1033 = tMOVri8 1 %reg1034 = tMOVri8 0 tCMPi8 %reg1029<kill>, 0 tBcc mbb<entry,0x8b06a10>, 0 Successors according to CFG: 0x8b06980 0x8b06a10 entry (0x8b06980, LLVM BB @0x8b01b30, ID#12): Predecessors according to CFG: 0x8b056f0 %reg1036 = tMOVrr %reg1034<kill> Successors according to CFG: 0x8b06a10 entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13): Predecessors according to CFG: 0x8b056f0 0x8b06980 %reg1024<dead> = tMOVrr %reg1030<kill> ... reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined, r1 live range from function entry to the tMOVrr instruction are dead. Eliminate r1 from the livein set of the entry BB, not the BB where the copy is. llvm-svn: 34866
-
- Mar 02, 2007
-
-
Evan Cheng authored
llvm-svn: 34843
-
- Mar 01, 2007
-
-
Evan Cheng authored
llvm-svn: 34768
-
Evan Cheng authored
llvm-svn: 34767
-
- Feb 26, 2007
-
-
Evan Cheng authored
llvm-svn: 34645
-
- Feb 25, 2007
-
-
Evan Cheng authored
llvm-svn: 34595
-
Evan Cheng authored
llvm-svn: 34594
-