This patch provides support for the MIPS relocations:

    *)  R_MIPS_GOT_HI16
    *)  R_MIPS_GOT_LO16
    *)  R_MIPS_CALL_HI16
    *)  R_MIPS_CALL_LO16

These are used for large GOT instruction sequences.

Contributer: Jack Carter
llvm-svn: 168471

llvm-svn: 168460

functions added in r168456.

llvm-svn: 168458

llvm-svn: 168456

llvm-svn: 168455

referring to a GOT entry.

llvm-svn: 168453

llvm-svn: 168450

llvm-svn: 168230

allowed in branch delay slot.

llvm-svn: 168131

support and use it in place of HasMips32r2Or64.

llvm-svn: 168089

llvm-svn: 168078

Patch by Sasa Stankovic.

llvm-svn: 167548

llvm-svn: 167546

instructions.

llvm-svn: 167348

llvm-svn: 167345

register is needed.

llvm-svn: 167341

reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.

llvm-svn: 167335

llvm-svn: 167315

This function estimates stack size and will be called before
PrologEpilogInserter scans the callee-saved registers.

llvm-svn: 167313

of the incoming argument area.

llvm-svn: 167312

"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.

llvm-svn: 167310

re-materialization of immediate loads.

llvm-svn: 167153

llvm-svn: 167107

use the caller's stack.

llvm-svn: 167048

information will be used by IsEligibleForTailCallOptimization to determine
whether a call can be tail-call optimized.

llvm-svn: 167043

for passing a function call argument on a stack.

llvm-svn: 167041

llvm-svn: 167039

We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.

llvm-svn: 166990

llvm-svn: 166960

llvm-svn: 166935

llvm-svn: 166903

All the credit goes to Jan Voung for noticing it was dead!

llvm-svn: 166902

Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as 
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.

The Mips16InstrInfo.td has been updated to use addr16 instead of addr.

The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.

llvm-svn: 166897

llvm-svn: 166852

arguments.

This is rather conservative and should be fixed later to be more aggressive.

llvm-svn: 166851

previous iteration.

llvm-svn: 166850

LowerFormalArguments in MipsTargetLowering.

No functionality change intended.

llvm-svn: 166846

of vararg functions back to the stack.

llvm-svn: 166844

This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.

llvm-svn: 166843

This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.

llvm-svn: 166841