Commits · b0ae36f0d1417136f1d38e69ee6504decbef8049 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Aug 04, 2015
- [AArch64] Vector FCOPYSIGN supports Custom-lowering: mark it as such. · b0ae36f0
  Ahmed Bougacha authored Aug 04, 2015
  b0ae36f0
- ARM: remove horrible printf left over from debugging · 9c340ec6
  Tim Northover authored Aug 03, 2015
  9c340ec6
Aug 03, 2015
- Convert some AArch64 code to foreach loops. NFC. · 7be8f8f0
  Pete Cooper authored Aug 03, 2015
  7be8f8f0
- ARM: prefer allocating VFP regs at stride 4 on Darwin. · 910dde7a
  Tim Northover authored Aug 03, 2015
  910dde7a
- [ARM] Make GlobalMerge merge extern globals by default · f3324cf1
  John Brawn authored Aug 03, 2015
  f3324cf1
- Be less conservative about forming IT blocks. · 6967e5e4
  James Molloy authored Aug 03, 2015
  6967e5e4
- WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, with type · fda53373
  JF Bastien authored Aug 03, 2015
  fda53373
Aug 02, 2015
- De-constify pointers to Type since they can't be modified. NFC · e3dcce97
  Craig Topper authored Aug 01, 2015
  e3dcce97
Aug 01, 2015
- [NVPTX] allow register copy between float and int · ffa09be2
  Jingyue Wu authored Aug 01, 2015
  ffa09be2
- -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11 · 78633802
  David Blaikie authored Aug 01, 2015
  78633802
- WebAssembly: handle more than int32 argument/return · 8f9aea08
  JF Bastien authored Aug 01, 2015
  8f9aea08
- -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11 · a5fd382e
  David Blaikie authored Aug 01, 2015
  a5fd382e
- AMDGPU/SI: Add implicit register operands in the correct order. · b4d0d6a3
  Alex Lorenz authored Jul 31, 2015
  b4d0d6a3
Jul 31, 2015
- [NVPTX] convert pointers in byval kernel arguments to global · cf70053b
  Jingyue Wu authored Jul 31, 2015
  cf70053b
- WebAssembly: handle `ret void`. · 4a2d5604
  JF Bastien authored Jul 31, 2015
  4a2d5604
- x86: check hasOpaqueSPAdjustment in canRealignStack · e71e653a
  JF Bastien authored Jul 31, 2015
  e71e653a
- WebAssembly: handle unused function arguments. · d7fcc6f9
  JF Bastien authored Jul 31, 2015
  d7fcc6f9
- WebAssembly: print basic integer assembly. · 600aee98
  JF Bastien authored Jul 31, 2015
  600aee98
- [x86] reassociate integer multiplies using machine combiner pass · 9ff46260
  Sanjay Patel authored Jul 31, 2015
  9ff46260
- [AArch64] Favor extended reg patterns for sub · 8a7ef3b2
  Geoff Berry authored Jul 31, 2015
  8a7ef3b2
- Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX · 4be014ae
  Jingyue Wu authored Jul 31, 2015
  4be014ae
- AMDGPU: Fix v16i32 to v16i8 truncstore · e1ce344b
  Matt Arsenault authored Jul 31, 2015
  e1ce344b
- AMDGPU/SI: Set DwarfRegNum · ba013379
  Matt Arsenault authored Jul 31, 2015
  ba013379
- AMDGPU/SI: Remove unused pattern for f32 constant loads · 82325598
  Tom Stellard authored Jul 31, 2015
  82325598
- [ARM] Lower modulo operation to generate __aeabi_divmod on Android · 532a1369
  Sumanth Gundapaneni authored Jul 31, 2015
  532a1369
Jul 30, 2015
- fix memcpy/memset/memmove lowering when optimizing for size · 1166f2ff
  Sanjay Patel authored Jul 30, 2015
  1166f2ff
- AMDGPU: Set SubRegIndex size and offset · 7a0c3a92
  Matt Arsenault authored Jul 30, 2015
  7a0c3a92
- AMDGPU: Fix unreachable when emitting binary debug info · b39e8583
  Matt Arsenault authored Jul 30, 2015
  b39e8583
- AMDGPU/SI: Simplify moveSMRDToVALU() · 4229aa94
  Tom Stellard authored Jul 30, 2015
  4229aa94
- AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo · 9d740760
  Tom Stellard authored Jul 30, 2015
  9d740760
- [mips][FastISel] Remove hidden mips-fast-isel option. · 2041b1dd
  Vasileios Kalintiris authored Jul 30, 2015
  2041b1dd
- [mips][FastISel] Apply only zero-extension to constants prior to their materialization. · 77fb0a3d
  Vasileios Kalintiris authored Jul 30, 2015
  77fb0a3d
- [X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm · cdb076b8
  Michael Kuperstein authored Jul 30, 2015
  cdb076b8
- push fast-math check for machine-combiner reassociations into instruction-type check; NFC · 5bfbb36a
  Sanjay Patel authored Jul 30, 2015
  5bfbb36a
- Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the... · c3890d29
  Nick Lewycky authored Jul 29, 2015
  c3890d29
- Rename hasCompatibleFunctionAttributes->areInlineCompatible based · d566fb12
  Eric Christopher authored Jul 29, 2015
  d566fb12
Jul 29, 2015
- [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit. · ba10f767
  Simon Pilgrim authored Jul 29, 2015
  ba10f767
- AArch64: use 32-bit MOV rather than UBFX to truncate registers. · 2a9d801f
  Tim Northover authored Jul 29, 2015
  2a9d801f
- [X86][SSE] Vectorize i64 ASHR operations · 86478c69
  Simon Pilgrim authored Jul 29, 2015
  86478c69
- Roll forward r242871 · 3a04dc6e
  Jingyue Wu authored Jul 29, 2015
  3a04dc6e