When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

llvm-svn: 77989

llvm-svn: 77754

 - Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019

llvm-svn: 75955

Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.

llvm-svn: 67511

subreg instructions.

llvm-svn: 61220

that of INSERT_SUBREG and SUBREG_TO_REG.

llvm-svn: 61218

llvm-svn: 61217

llvm-svn: 61216

llvm-svn: 59841

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56596

llvm-svn: 56475

llvm-svn: 56469

llvm-svn: 55779

llvm-svn: 55049

LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444

Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.

llvm-svn: 53746

It's not safe to remove SUBREG_TO_REG that looks like identity copies, e.g. movl %eax, %eax on x86-64 actually does a zero-extend.

llvm-svn: 52421

llvm-svn: 52373

llvm-svn: 51949

llvm-svn: 51933

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48223

llvm-svn: 48221

llvm-svn: 48167

Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130

llvm-svn: 46930

Machine-level API cleanup instigated by Chris.

llvm-svn: 45470

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

llvm-svn: 45418

llvm-svn: 43249

Tested with "make check"!

llvm-svn: 42346

isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958

Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.

llvm-svn: 41005

llvm-svn: 40863

Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.

llvm-svn: 40521