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  1. May 01, 2012
  2. Apr 16, 2012
    • Chandler Carruth's avatar
      Flip the new block-placement pass to be on by default. · 4190b507
      Chandler Carruth authored
      This is mostly to test the waters. I'd like to get results from FNT
      build bots and other bots running on non-x86 platforms.
      
      This feature has been pretty heavily tested over the last few months by
      me, and it fixes several of the execution time regressions caused by the
      inlining work by preventing inlining decisions from radically impacting
      block layout.
      
      I've seen very large improvements in yacr2 and ackermann benchmarks,
      along with the expected noise across all of the benchmark suite whenever
      code layout changes. I've analyzed all of the regressions and fixed
      them, or found them to be impossible to fix. See my email to llvmdev for
      more details.
      
      I'd like for this to be in 3.1 as it complements the inliner changes,
      but if any failures are showing up or anyone has concerns, it is just
      a flag flip and so can be easily turned off.
      
      I'm switching it on tonight to try and get at least one run through
      various folks' performance suites in case SPEC or something else has
      serious issues with it. I'll watch bots and revert if anything shows up.
      
      llvm-svn: 154816
      4190b507
  3. Mar 29, 2012
  4. Mar 28, 2012
  5. Mar 14, 2012
    • Andrew Trick's avatar
      misched: implemented a framework for top-down or bottom-up scheduling. · 8823decd
      Andrew Trick authored
      New flags: -misched-topdown, -misched-bottomup. They can be used with
      the default scheduler or with -misched=shuffle. Without either
      topdown/bottomup flag -misched=shuffle now alternates scheduling
      direction.
      
      LiveIntervals update is unimplemented with bottom-up scheduling, so
      only -misched-topdown currently works.
      
      Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class.
      ScheduleDAGMI is aware of the top and bottom of the unscheduled zone
      within the current region. Scheduling policy can be plugged into
      the ScheduleDAGMI driver by implementing MachineSchedStrategy.
      ConvergingScheduler is now the default scheduling algorithm.
      It exercises the new driver but still does no reordering.
      
      llvm-svn: 152700
      8823decd
  6. Feb 21, 2012
  7. Feb 16, 2012
  8. Feb 15, 2012
    • Andrew Trick's avatar
      Revert r150565 again. Appears to be a stage2 failure with dragonegg. · 899f46c1
      Andrew Trick authored
      I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it.
      
      llvm-svn: 150568
      899f46c1
    • Andrew Trick's avatar
      Reapply r150565 with the typo fix properly merged. · 56d412a1
      Andrew Trick authored
      llvm-svn: 150567
      56d412a1
    • Andrew Trick's avatar
      reverting r150565. Premature push. · dd5beb78
      Andrew Trick authored
      llvm-svn: 150566
      dd5beb78
    • Andrew Trick's avatar
      d83284c1
    • Andrew Trick's avatar
      Allow CodeGen (llc) command line options to work as expected. · e9a951c0
      Andrew Trick authored
      The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes.
      
      A target has two ways of overriding standard passes:
      1) Redefine the pass pipeline (override TargetPassConfig::add%Stage)
      2) Replace or suppress individiual passes with TargetPassConfig::substitutePass.
      
      In both cases, the command line options associated with the pass override the target default.
      
      For example, say a target wants to disable machine instruction scheduling by default:
      
      - The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods.
      
      - Without any llc options, no scheduler is run.
      
      - With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing.
      
      Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day...
      
      I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well.
      
      llvm-svn: 150563
      e9a951c0
    • Andrew Trick's avatar
      Added TargetPassConfig::disablePass/substitutePass as a general mechanism to... · c9ce9d23
      Andrew Trick authored
      Added TargetPassConfig::disablePass/substitutePass as a general mechanism to override specific passes.
      
      llvm-svn: 150562
      c9ce9d23
  9. Feb 11, 2012
    • Andrew Trick's avatar
      Add TargetPassConfig hooks for scheduling/bundling. · ee874db8
      Andrew Trick authored
      In case the MachineScheduling pass I'm working on doesn't work well
      for another target, they can completely override it. This also adds a
      hook immediately after the RegAlloc pass to cleanup immediately after
      vregs go away. We may want to fold it into the postRA hook later.
      
      llvm-svn: 150298
      ee874db8
  10. Feb 10, 2012
    • Andrew Trick's avatar
      comment grammar · 09fc1bb6
      Andrew Trick authored
      llvm-svn: 150233
      09fc1bb6
    • Andrew Trick's avatar
      RegAlloc superpass: includes phi elimination, coalescing, and scheduling. · d3f8fe81
      Andrew Trick authored
      Creates a configurable regalloc pipeline.
      
      Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
      
      When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
      
      CodeGen transformation passes are never "required" as an analysis
      
      ProcessImplicitDefs does not require LiveVariables.
      
      We have a plan to massively simplify some of the early passes within the regalloc superpass.
      
      llvm-svn: 150226
      d3f8fe81
  11. Feb 09, 2012
  12. Feb 08, 2012
  13. Feb 04, 2012
  14. Nov 12, 2011
  15. Apr 30, 2011
  16. Apr 19, 2011
  17. Jun 03, 2010
  18. May 28, 2010
  19. Feb 18, 2010
  20. May 13, 2008
  21. May 06, 2008
  22. Dec 29, 2007
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