because it's more likely to keep debug line information in its original
order.

llvm-svn: 108496

occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).

llvm-svn: 108484

llvm-svn: 108478

the function. We'll just turn it into a "trap" instruction instead.

The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:

$ cat t.ll
define void @foo() {
entry:
  unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
        .section        __TEXT,__text,regular,pure_instructions
        .globl  _foo
        .align  4, 0x90
_foo:                                   ## @foo
Leh_func_begin0:
## BB#0:                                ## %entry
        pushq   %rbp
Ltmp0:
        movq    %rsp, %rbp
Ltmp1:
Leh_func_end0:
...

The unwind tables then have bad data in them causing all sorts of problems.

Fixes <rdar://problem/8096481>.

llvm-svn: 108473

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

to keep "Text" in sync with the "pure instructions" section attribute.
Lack of this attribute was preventing the assembler from emitting
multibyte noops instructions for templates (and inlines, and other
coalesced stuff) and was causing the assembler to mismatch .o files.

This fixes rdar://8018335

llvm-svn: 108461

llvm-svn: 108452

llvm-svn: 108450

make sure to allocate enough space in the std::vector.

llvm-svn: 108449

llvm-svn: 108448

llvm-svn: 108441

llvm-svn: 108440

llvm-svn: 108438

llvm-svn: 108419

llvm-svn: 108413

get *very* large, but we only need it to be the size of the number of pregs.

llvm-svn: 108412

get *very* large, but we only need it to be the size of thenumber of pregs.

llvm-svn: 108411

follow on to r103765

llvm-svn: 108390

llvm-svn: 108381

independent of the order that isel happens to visit the dbg_declare
intrinsics. This fixes a bug in which the formal arguments were
being printed in reverse order, now that fast isel is going bottom up.

llvm-svn: 108369

llvm-svn: 108364

it can look past points where a debugger might modify user variables.

llvm-svn: 108336

Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.

llvm-svn: 108304

constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302

llvm-svn: 108277

This may not be right in all cases, but it's better
than asserting which it was doing before.  PR 7528.

llvm-svn: 108268

LiveInterval::overlapsFrom dereferences end() if it is called on an empty
interval.

It would be reasonable to just return false - an empty interval doesn't overlap
anything, but I want to know who is doing it first.

llvm-svn: 108264

Also, one binary search is enough.

llvm-svn: 108261

they already have one.

This fixes the himenobmtxpa miscompilation on ARM.

The PostRA scheduler got confused by the double memoperand and hoisted a stack
slot load above a store to the same slot.

llvm-svn: 108219

llvm-svn: 108164

llvm-svn: 108130

AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.

With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.

llvm-svn: 108122

physical register can be allocated in the class of the virtual are sufficient.

I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.

llvm-svn: 108118

getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115

intended functionality change.

The avoidance of hoistiing implicitdef seems wrong though.

llvm-svn: 108109

Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

llvm-svn: 108095

The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

llvm-svn: 108093

assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.

llvm-svn: 108088

This doesn't change the behavior of SelectBitcast for X86.

llvm-svn: 108073

correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072