After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 74385

llvm-svn: 74384

llvm-svn: 74382

target-specific operand printing functionality.  Yay.

llvm-svn: 74379

llvm-svn: 74378

llvm-svn: 74377

llvm-svn: 74375

a base register.  We just ignore it for now.

llvm-svn: 74374

globals.  This implements remat-constant.ll even without aggressive-remat.

llvm-svn: 74373

implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.

llvm-svn: 74372

llvm-svn: 74368

llvm-svn: 74366

llvm-svn: 74357

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.

llvm-svn: 74350

Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.

llvm-svn: 74336

llvm-svn: 74334

llvm-svn: 74332

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

llvm-svn: 74328

llvm-svn: 74327

llvm-svn: 74326

llvm-svn: 74322

llvm-svn: 74321

llvm-svn: 74316

llvm-svn: 74315

llvm-svn: 74313

llvm-svn: 74310

llvm-svn: 74293

Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288

llvm-svn: 74277

llvm-svn: 74275

llvm-svn: 74272

invalid characters like backslashes on Windows. Patch by James Abbatiello!

llvm-svn: 74265

llvm-svn: 74255

llvm-svn: 74253

llvm-svn: 74246

llvm-svn: 74241

llvm-svn: 74239