llvm-svn: 135939

llvm-svn: 135930

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

llvm-svn: 134546

llvm-svn: 134024

llvm-svn: 133846

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

llvm-svn: 122247

llvm-svn: 122246

pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536

 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039

When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.

For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.

llvm-svn: 100559

On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.

The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.

This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.

The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.

llvm-svn: 99524

This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345

llvm-svn: 98220

llvm-svn: 96763

We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059

llvm-svn: 96038

llvm-svn: 95438

-enable-new-x86-encoder until its stable.

llvm-svn: 95256

llvm-svn: 95254

llvm-svn: 95144

No functionality change.

llvm-svn: 90336

 - Note, this is a gigantic hack, with the sole purpose of unblocking further
   work on the assembler (its also possible to test the mathcer more completely
   now).

 - Despite being a hack, its actually good enough to work over all of 403.gcc
   (although some encodings are probably incorrect). This is a testament to the 
   beauty of X86's MachineInstr, no doubt! ;)

llvm-svn: 80234

 - Less boilerplate == good.

llvm-svn: 77052

llvm-svn: 76344

--- Reverse-merging r75799 into '.':
 U   test/Analysis/PointerTracking
U    include/llvm/Target/TargetMachineRegistry.h
U    include/llvm/Target/TargetMachine.h
U    include/llvm/Target/TargetRegistry.h
U    include/llvm/Target/TargetSelect.h
U    tools/lto/LTOCodeGenerator.cpp
U    tools/lto/LTOModule.cpp
U    tools/llc/llc.cpp
U    lib/Target/PowerPC/PPCTargetMachine.h
U    lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U    lib/Target/PowerPC/PPCTargetMachine.cpp
U    lib/Target/PowerPC/PPC.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/ARMTargetMachine.h
U    lib/Target/ARM/ARM.h
U    lib/Target/XCore/XCoreTargetMachine.cpp
U    lib/Target/XCore/XCoreTargetMachine.h
U    lib/Target/PIC16/PIC16TargetMachine.cpp
U    lib/Target/PIC16/PIC16TargetMachine.h
U    lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U    lib/Target/Alpha/AlphaTargetMachine.cpp
U    lib/Target/Alpha/AlphaTargetMachine.h
U    lib/Target/X86/X86TargetMachine.h
U    lib/Target/X86/X86.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.h
U    lib/Target/CppBackend/CPPTargetMachine.h
U    lib/Target/CppBackend/CPPBackend.cpp
U    lib/Target/CBackend/CTargetMachine.h
U    lib/Target/CBackend/CBackend.cpp
U    lib/Target/TargetMachine.cpp
U    lib/Target/IA64/IA64TargetMachine.cpp
U    lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U    lib/Target/IA64/IA64TargetMachine.h
U    lib/Target/IA64/IA64.h
U    lib/Target/MSIL/MSILWriter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.h
U    lib/Target/CellSPU/SPU.h
U    lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.cpp
U    lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U    lib/Target/Mips/MipsTargetMachine.cpp
U    lib/Target/Mips/MipsTargetMachine.h
U    lib/Target/Mips/Mips.h
U    lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U    lib/Target/Sparc/SparcTargetMachine.cpp
U    lib/Target/Sparc/SparcTargetMachine.h
U    lib/ExecutionEngine/JIT/TargetSelect.cpp
U    lib/Support/TargetRegistry.cpp

llvm-svn: 75820

Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.

llvm-svn: 75799

 - This abuses TargetMachineRegistry's constructor for now, this will get
   cleaned up in time.

llvm-svn: 75762

Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.

llvm-svn: 75670

cleanup, removed some #includes and moved Object Code Emitter out-of-line.

llvm-svn: 74813

 - This more or less amounts to a revert of r65379. I'm curious to know what
   happened that caused this variable to become unused.

llvm-svn: 74579

llvm-svn: 72697

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631

which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440

Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343

llvm-svn: 70275

use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270

llvm-svn: 67668