simultaneously.  Move that pass to SimpleRegisterCoalescing.

This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.

llvm-svn: 37520

certain linkers...

llvm-svn: 36944

llvm-svn: 36662

Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652

llvm-svn: 36632

llvm-svn: 36452

llvm-svn: 36431

long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218

llvm-svn: 35208

llvm-svn: 34593

llvm-svn: 34428

Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399

llvm-svn: 34382

llvm-svn: 34342

llvm-svn: 32698

is 'unsigned'.

llvm-svn: 32279

llvm-svn: 32251

llvm-svn: 32113

a #include of iostream.

llvm-svn: 31800

llvm-svn: 31561

llvm-svn: 31500

llvm-svn: 31153

llvm-svn: 29911

llvm-svn: 29471

llvm-svn: 29434

llvm-svn: 29220

llvm-svn: 28973

that still fails (because all the register spill weights are inf), just grab
one.

llvm-svn: 28262

llvm-svn: 28219

the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.

llvm-svn: 28217

llvm-svn: 27133

llvm-svn: 26328

llvm-svn: 25515

llvm-svn: 25031

do it. :)

    <_sabre_> excuses excuses

llvm-svn: 24471

asserts.

llvm-svn: 24445

llvm-svn: 23400

This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll

llvm-svn: 23158

Use this information to avoid doing expensive interval intersections for
registers that could not possible be interesting.  This speeds up linscan
on ia64 compiling kc++ in release mode from taking 7.82s to 4.8s(!), total
itanium llc time on this program is 27.3s now.  This marginally speeds up
PPC and X86, but they appear to be limited by other parts of linscan, not
this code.

On this program, on itanium, live intervals now takes 41% of llc time.

llvm-svn: 22986

number of regs (e.g. most riscs), many functions won't need to use callee
clobbered registers.  Do a speculative check to see if we can get a free
register without processing the fixed list (which has all of these).  This
saves a lot of time on machines with lots of callee clobbered regs (e.g.
ppc and itanium, also x86).

This reduces ppc llc compile time from 184s -> 172s on kc++.  This is probably
worth FAR FAR more on itanium though.

llvm-svn: 22972