llvm-svn: 117984

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117975

llvm-svn: 117964

llvm-svn: 117955

bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953

at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950

llvm-svn: 117941

llvm-svn: 117940

llvm-svn: 117939

llvm-svn: 117938

llvm-svn: 117937

llvm-svn: 117935

llvm-svn: 117932

llvm-svn: 117930

llvm-svn: 117929

llvm-svn: 117922

llvm-svn: 117911

peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905

llvm-svn: 117903

must be 8 bits.  Support this memory form.

llvm-svn: 117902

aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901

llvm-svn: 117900

in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897

for shl.  Caught by inspection.

llvm-svn: 117820

llvm-svn: 117803

consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

conditional. Check for those instructions explicitly.

llvm-svn: 117747

llvm-svn: 117745

just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735

This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

llvm-svn: 117721

llvm-svn: 117720

Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

llvm-svn: 117719

Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation.

llvm-svn: 117712

llvm-svn: 117708

llvm-svn: 117704

llvm-svn: 117699

llvm-svn: 117696

llvm-svn: 117694