and add Mips64's version too.

llvm-svn: 144018

floating pointer registers.

llvm-svn: 144016

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

llvm-svn: 142220

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

llvm-svn: 141476

llvm-svn: 141475

llvm-svn: 141474

conversion instructions. 

llvm-svn: 141473

It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735

multiclasses.

llvm-svn: 140731

llvm-svn: 140705

llvm-svn: 140704

llvm-svn: 140661

of the instruction definitions using Pat<>.

llvm-svn: 140644

complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354

llvm-svn: 139405

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

llvm-svn: 132718

llvm-svn: 131927

llvm-svn: 131233

Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.

llvm-svn: 129594

Luis Felipe Strano Moraes!

llvm-svn: 129558

llvm-svn: 128650

llvm-svn: 127003

llvm-svn: 122513

llvm-svn: 111241

llvm-svn: 99737

llvm-svn: 94914

llvm-svn: 88887

llvm-svn: 86895

llvm-svn: 86651

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

llvm-svn: 72483

Handle odd registers allocation in FGR32.

llvm-svn: 67422

llvm-svn: 54315

access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

llvm-svn: 54229