Apparently dragonegg uses it.

llvm-svn: 187454

In limited testing this seems to work. Caveat emptor.

llvm-svn: 187452

llvm-svn: 187448

Call into ComputeMaskedBits to figure out which bits are set on both add
operands and determine if the value is a power-of-two-or-zero or not.

llvm-svn: 187445

It will now only convert the arguments / return value and call
the underlying function if the types are able to be bitcasted.
This avoids using fp<->int conversions that would occur before.

llvm-svn: 187444

llvm-svn: 187443

llvm-svn: 187442

llvm-svn: 187441

turns "bal" into "bgezal".

llvm-svn: 187440

llvm-svn: 187439

llvm-svn: 187438

llvm-svn: 187437

When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.

This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.

llvm-svn: 187436

llvm-svn: 187435

register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.

llvm-svn: 187433

This is a follow up patch for r187390 to implement the parser for the
Windows-style command line. This should follow the rule as described
at http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.85).aspx

Differential Revision: http://llvm-reviews.chandlerc.com/D1235

llvm-svn: 187430

- Thanks to Ilia Filippov for pointing out the inconsistency!

llvm-svn: 187424

llvm-svn: 187421

This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.

llvm-svn: 187410

llvm-svn: 187406

When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.

Split the check of the value of the second operands to the ands.  Move the cast
and variable declaration slightly higher to make it slightly easier to follow.

Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 187404

llvm-svn: 187403

llvm-svn: 187402

This is the first of many upcoming patches for PowerPC fast
instruction selection support.  This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass.  It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch.  There will
be quite a few tests coming with future patches.

This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only.  It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation.  This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.

This patch has been tested by building and running the
projects/test-suite code with -O0.  All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.

llvm-svn: 187399

build_vector is lowered to REG_SEQUENCE, which is something the register
allocator does a good job at optimizing.

llvm-svn: 187397

This patch prevents the following combine when the input vector is used more
than once.
insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx
=>
build_vector elt0, ..., NewEltIdx, ..., eltN 

The reasons are:
- Building a vector may be expensive, so try to reuse the existing part of a
  vector instead of creating a new one (think big vectors).
- elt0 to eltN now have two users instead of one. This may prevent some other
  optimizations.

llvm-svn: 187396

The problem is due to the section name being explicitly mentioned in
the IR and differing between the two platforms.

llvm-svn: 187394

update testcase to make sure we generate debug info for walrus
by adding a non-trivial constructor and verify that we don't
emit an ODR signature for the type.

llvm-svn: 187393

sure the comments for each testcase are a bit easier to distinguish.

llvm-svn: 187392

odr hashes.

llvm-svn: 187391

llvm-svn: 187385

llvm-svn: 187383

llvm-svn: 187380

This will let us use getUniqueID instead of st_dev directly on clang.

llvm-svn: 187378

llvm-svn: 187375

llvm-svn: 187371

Thanks Eric.

llvm-svn: 187368

llvm-svn: 187363

llvm-svn: 187362

32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.

llvm-svn: 187356