Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

llvm-svn: 132063

offsets that are larger than 0x10000.

llvm-svn: 132003

llvm-svn: 131233

Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086

llvm-svn: 130131

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

llvm-svn: 128650

llvm-svn: 127034

Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka

llvm-svn: 127032

llvm-svn: 127027

llvm-svn: 127005

llvm-svn: 127003

llvm-svn: 123760

llvm-svn: 122513

llvm-svn: 121377

Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again

llvm-svn: 121164

(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163

llvm-svn: 118864

llvm-svn: 118667

llvm-svn: 118515

llvm-svn: 111468

llvm-svn: 111241

llvm-svn: 106465

need them.

llvm-svn: 98937

llvm-svn: 97374

llvm-svn: 96504

in hte generated dag isel fil.

llvm-svn: 96193

the instruction to load those args removed. This fix PR6071

llvm-svn: 93880

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610

llvm-svn: 72483

llvm-svn: 60487

parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.

llvm-svn: 54724

llvm-svn: 54516

Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.

llvm-svn: 54403