Radar 9012638.

llvm-svn: 126127

The DAGCombiner folds the zext into complex load instructions. This patch
prevents this optimization on vectors since none of the supported targets
knows how to perform load+vector_zext in one instruction.

llvm-svn: 126080

Do not emit empty DW_TAG_lexical_block DIEs.  In one test case, size of debug info reduced by almost 7%.

llvm-svn: 126009

llvm-svn: 126005

llvm-svn: 126003

llvm-svn: 126002

llvm-svn: 126001

Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.
This time with a fix that avoids using invalidated DenseMap iterator.

llvm-svn: 125984

All new virtual registers created for spilling or splitting point back to their original.

llvm-svn: 125980

llvm-svn: 125968

The rewriter works almost identically to -rewriter=trivial, except it also
eliminates any identity copies.

This makes the new register allocators independent of VirtRegRewriter.cpp which
will be going away at the same time as RegAllocLinearScan.

llvm-svn: 125967

llvm-svn: 125960

llvm-svn: 125830

llvm-svn: 125802

Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.

llvm-svn: 125794

llvm-svn: 125789

A local live range is live in a single basic block. If such a range fails to
allocate, try to find a sub-range that would get a larger spill weight than its
interference.

llvm-svn: 125764

the time but presumably my email got lost).  Examples where the previous logic
got it wrong: (1) a signed i8 multiply of 64 by 2 overflows, but the high part is
zero; (2) a signed i8 multiple of -128 by 2 overflows, but the high part is all
ones. 

llvm-svn: 125748

llvm-svn: 125728

llvm-svn: 125727

llvm-svn: 125726

other getNode() methods.  Radar 9002173.

llvm-svn: 125665

llvm-svn: 125651

transformation if we can't legally create a build vector of the correct
type. Check that we can make the transformation first, and add a TODO to
refactor this code with similar cases.

Fixes: PR9223 and rdar://9000350
llvm-svn: 125631

llvm-svn: 125625

Ignore DBG_VALUE machine instructions while constructing instruction ranges based on location info. 
Machine instruction range consisting of only DBG_VALUE MIs only contributes consecutive labels in assembly output, which is harmless, and empty scope entry in DebugInfo, which confuses debugger tools.

llvm-svn: 125577

llvm-svn: 125563

llvm-svn: 125552

llvm-svn: 125537

Simplify the spill weight calculation a bit by bypassing
getApproximateInstructionCount() and using LiveInterval::getSize() directly.
This changes the computed spill weights, but only by a constant factor in each
function. It should not affect how spill weights compare against each other, and
so it shouldn't affect code generation.

llvm-svn: 125530

section.

llvm-svn: 125526

Fix PR8854. Track inserted copies to avoid read before write. Sorry, it's hard to reduce a sensible small test case.

llvm-svn: 125523

builders unhappy.

llvm-svn: 125504

llvm-svn: 125490

idiom.  Change various clients to simplify their code.

llvm-svn: 125487

vector fp conversions.

llvm-svn: 125482

llvm-svn: 125481

llvm-svn: 125477

llvm-svn: 125476

have their low bits set to zero.  This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively.  Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST).  The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.

llvm-svn: 125470