llvm-svn: 14412

llvm-svn: 14411

* Use MachineBB's built-in numbering system instead of reinventing one

llvm-svn: 14408

* Remove x86-specific comment re: intel vs. at&t assembly syntax

llvm-svn: 14406

llvm-svn: 14405

* Replace silent fall-through FIXME comments with an error to cerr and an abort
* No need to set size of statically initialized arrays

llvm-svn: 14404

llvm-svn: 14403

Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

llvm-svn: 14389

llvm-svn: 14387

llvm-svn: 14386

llvm-svn: 14385

* Parenthesize assert() expressions correctly
* Fix spacing around for() and if() statements

llvm-svn: 14384

* Wrap long line to 80 cols

llvm-svn: 14382

* Send an error message to std::cerr before abort()ing

llvm-svn: 14381

* Remove unnecessary parens, braces, clean up code layout

llvm-svn: 14379

llvm-svn: 14377

llvm-svn: 14376

more operand in GEPOps than there are types in GEPTypes: the pointer that is the
first operand of the GEP instruction.

llvm-svn: 14375

llvm-svn: 14372

(It's not yet clear how to copy doubles from register to register.)

llvm-svn: 14371

* Use the DEBUG() guard for debug printouts

llvm-svn: 14367

llvm-svn: 14366

Compactify the code that emits copies of constant ints into registers.

llvm-svn: 14365

llvm-svn: 14364

Fix bug in emitGEPOperation where we weren't passing MBB, IP to getReg.
(hey, wouldn't a constant expression lowering pass be cool? huh huhuhuh)
Fix bug in emitGEPOperation where we might try to OR a constant into a
register which was too big to fit in the immediate field.
Support and, or, xor of longs.

llvm-svn: 14363

variant worth worrying about; the fp ones have two.

llvm-svn: 14362

variant worth worrying about; the fp ones have two.
Add fp stores.

llvm-svn: 14361

variant worth worrying about; the fp ones have two.
Stub out the case analysis of int-to-fp casts (no code yet).
I think the number of operands passed to BuildMI for loads was wrong.
Support load and store of float and double.

llvm-svn: 14360

representational consistency, we want to address the halves of each 64-bit value
separately.

llvm-svn: 14356

llvm-svn: 14355

instructions they augment, instead of replacing them.  It's good for debugging,
and it's OK for the sparcv9 backend.

llvm-svn: 14353

llvm-svn: 14332

llvm-svn: 14305

them with a namespace declaration.

llvm-svn: 14303

llvm-svn: 14302

llvm-svn: 14301

llvm-svn: 14300

llvm-svn: 14299

llvm-svn: 14298

llvm-svn: 14297