Turn this:
movswl  %ax, %eax
movl    %eax, -36(%ebp)
xorl    %edi, -36(%ebp)
into
movswl  %ax, %eax
xorl    %edi, %eax
movl    %eax, -36(%ebp)
by unfolding the load / store xorl into an xorl and a store when we know the
value in the spill slot is available in a register. This doesn't change the
number of instructions but reduce the number of times memory is accessed.

Also unfold some load folding instructions and reuse the value when similar
situation presents itself.

llvm-svn: 42947

llvm-svn: 42945

for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934

llvm-svn: 42924

llvm-svn: 42919

llvm-svn: 42916

function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908

llvm-svn: 42907

is a scalar integer.

llvm-svn: 42906

llvm-svn: 42903

(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.

llvm-svn: 42899

llvm-svn: 42898

llvm-svn: 42888

may be overloaded with vector types. And add a testcase for codegen for
these.

llvm-svn: 42885

Factor out the code that expands the "nasty scalar code" for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.

Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.

llvm-svn: 42884

Make ppc long double constants print.

llvm-svn: 42882

llvm-svn: 42880

llvm-svn: 42879

enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

No compile-time support for constant operations yet,
just format transformations.  Make readers and
writers work.  Split constants into 2 doubles in
Legalize.

llvm-svn: 42865

llvm-svn: 42824

Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).

llvm-svn: 42822

llvm-svn: 42821

Fix an extremely stupid bug that prevented first round of coalescing (physical registers only) from happening.

llvm-svn: 42820

for consistency.

llvm-svn: 42769

use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762

Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.

llvm-svn: 42759

and individual SDOperand operands.

llvm-svn: 42753

optimization passes.

llvm-svn: 42749

llvm-svn: 42742

input.  APInt unfortunately zero-extends signed integers, so Dale
modified the function to expect zero-extended input.  Make this
assumption explicit in the function name.

llvm-svn: 42732

llvm-svn: 42692

llvm-svn: 42686

(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677

although not well, and shortening FP converts.

llvm-svn: 42672

basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.

llvm-svn: 42644

llvm-svn: 42636

llvm-svn: 42635

llvm-svn: 42634

llvm-svn: 42627