not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.

llvm-svn: 99435

llvm-svn: 99434

llvm-svn: 99428

llvm-svn: 99423

NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415

N3VX instructions using special case code.

llvm-svn: 99409

llvm-svn: 99402

llvm-svn: 99376

and defining the add pattern with Pat<>, eliminating a use of
parallel.

llvm-svn: 99375

respectively, and add some more comment.

llvm-svn: 99373

llvm-svn: 99370

ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.

llvm-svn: 99369

llvm-svn: 99360

llvm-svn: 99359

llvm-svn: 99358

test run permformance numbers say as to whether it helps.

llvm-svn: 99355

This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352

just use an empty result list.

llvm-svn: 99346

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345

llvm-svn: 99344

llvm-svn: 99328

llvm-svn: 99327

Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326

llvm-svn: 99322

Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

llvm-svn: 99320

These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309

llvm-svn: 99295

Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288

llvm-svn: 99266

of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265

of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261

MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.

llvm-svn: 99249

MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.

llvm-svn: 99248

llvm-svn: 99245

llvm-svn: 99201

llvm-svn: 99192

corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189

llvm-svn: 99187

specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185

Thanks, Chris!

llvm-svn: 99183