llvm-svn: 76963

llvm-svn: 76962

eliminating isNamed.

llvm-svn: 76946

%0 = malloc [3758096384 x i32]

The "malloc" instruction doesn't support 64-bits correctly (see PR715),
and should be removed.  Victor is actively working on fixing this, in 
the meantime just don't crash.

llvm-svn: 76899

 - Yay for '-'s and simplifications!

 - I kept StringMap::GetOrCreateValue for compatibility purposes, this can
   eventually go away. Likewise the StringMapEntry Create functions still follow
   the old style.

 - NIFC.

llvm-svn: 76888

llvm-svn: 76865

llvm-svn: 76849

Reorder if-else branches as suggested by Bill.

llvm-svn: 76808

Constify the key in Mi2IndexMap.

llvm-svn: 76801

llvm-svn: 76799

simplification.
 - NFC

llvm-svn: 76789

Put comment printing under asm-verbose.

llvm-svn: 76780

Make some changes suggested by Bill and Evan.

llvm-svn: 76775

a new getSectionForMergableConstant hook.  This removes one dependence
of TAI on Type, and provides the hook with enough info to make the 
right decision based on whether the global has relocations etc.

llvm-svn: 76705

Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.

This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.

llvm-svn: 76703

llvm-svn: 76702

Constant::getRelocationInfo(), which has a much simpler
to use API.  It still should not be part of libvmcore, but
is better than it was.  Also teach it to be smart about 
hidden visibility.

llvm-svn: 76700

llvm-svn: 76688

Add some support for iterative coalescers to calculate a joined live
range's weight properly.  This is turned off right now in the sense that
you'll get an assert if you get into a situation that can only be caused
by an iterative coalescer.  All other code paths operate exactly as
before so there is no functional change with this patch.  The asserts
should be disabled if/when an iterative coalescer gets added to trunk.

llvm-svn: 76680

llvm-svn: 76679

pool entry will require relocations against it.  I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.

llvm-svn: 76678

their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address

llvm-svn: 76672

llvm-svn: 76646

be useful, and it's currently unused.  (Some issues: it isn't actually 
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)

llvm-svn: 76633

Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604

Add PrefixPrinter arguments to the dump routines for MachineFunction and
MachineBasicBlock.  We'll use these shortly.

llvm-svn: 76603

llvm-svn: 76598

LLVM IR concept.

llvm-svn: 76590

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

llvm-svn: 76558

llvm-svn: 76553

global declared symbols are initialized with references from other global
symbols.

llvm-svn: 76540

Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))

llvm-svn: 76535

llvm-svn: 76533

llvm-svn: 76519

to a place where it affects everything.  Occurs
only on calls AFAIK.

llvm-svn: 76502

llvm-svn: 76480

"LinkerPrivatePrefix". It seems to have been used in only one place before I
started this "linker_private" business. I'm thinking that a rename is in
order...

llvm-svn: 76479

llvm-svn: 76472

Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.

llvm-svn: 76458