llvm-svn: 30039

llvm-svn: 30038

llvm-svn: 29965

llvm-svn: 29962

or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957

- Also disable isel load folding if -fast.

llvm-svn: 29956

handling.)

llvm-svn: 29954

llvm-svn: 29953

llvm-svn: 29952

there are clearly some encoding bugs lurking in there somewhere.

llvm-svn: 29949

llvm-svn: 29946

Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions.

llvm-svn: 29943

Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.

llvm-svn: 29934

llvm-svn: 29911

SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907

ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.

llvm-svn: 29903

llvm-svn: 29901

llvm-svn: 29898

llvm-svn: 29895

llvm-svn: 29894

llvm-svn: 29891

llvm-svn: 29889

asm printer will print it as offset*4. e.g. bne cr0, $+8.

The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.

llvm-svn: 29885

llvm-svn: 29880

store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876

_swap_16:
        slwi r2, r3, 24
        rlwimi r2, r3, 8, 8, 15
        srwi r3, r2, 16
        blr

now.

llvm-svn: 29864

llvm-svn: 29863

implement a movcond instruction

llvm-svn: 29857

llvm-svn: 29856

llvm-svn: 29854

does emit linkable .o files in very simple cases.

llvm-svn: 29850

llvm-svn: 29814

llvm-svn: 29802

llvm-svn: 29793

llvm-svn: 29780

llvm-svn: 29756

llvm-svn: 29752

llvm-svn: 29751

llvm-svn: 29750

llvm-svn: 29748