llvm-svn: 182531

Now that return value registers are return instruction uses, there is no
need for special treatment of return blocks.

llvm-svn: 174416

llvm-svn: 170902

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131

This saves a bit of memory.

llvm-svn: 168852

Clients can use the equivalent functions in MRI.

llvm-svn: 165990

Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

llvm-svn: 152016

llvm-svn: 152001

llvm-svn: 151996

AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit

llvm-svn: 148260

opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
        movl    %eax, %ecx
        movl    %ecx, %eax
        ret

The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)

This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.

rdar://10428165
rdar://10640363

llvm-svn: 147716

generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

llvm-svn: 134259

llvm-svn: 133944

No functional change was intended.

llvm-svn: 133202

llvm-svn: 132487

Luis Felipe Strano Moraes!

llvm-svn: 129558

llvm-svn: 121805

llvm-svn: 112832

make sure to allocate enough space in the std::vector.

llvm-svn: 108449

llvm-svn: 108448

llvm-svn: 108440

llvm-svn: 108419

llvm-svn: 108413

get *very* large, but we only need it to be the size of the number of pregs.

llvm-svn: 108412

AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.

With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.

llvm-svn: 108122

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

for debug information.

llvm-svn: 105324

llvm-svn: 105300

and End arguments by-value rather than by-reference.

llvm-svn: 101830

llvm-svn: 100904

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

llvm-svn: 92837

Change errs() to dbgs().

llvm-svn: 92093

llvm-svn: 90970

<rdar://problem/6721894>. Allow multiple registers to be renamed together (super and sub) if necessary to break an anti-dependence.

llvm-svn: 89722

llvm-svn: 89511