- Dec 03, 2012
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Chandler Carruth authored
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
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- Jun 21, 2012
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Jakob Stoklund Olesen authored
Stop depending on the LiveIntervalUnions in RegAllocBase, they are about to be removed. The changes are mostly replacing register alias iterators with regunit iterators, and querying LiveRegMatrix instrad of RegAllocBase. InterferenceCache is converted to work with per-regunit LiveIntervalUnions, and it checks fixed regunit interference separately, using the fixed live intervals provided by LiveIntervalAnalysis. The local splitting helper calcGapWeights() is also considering fixed regunit interference which is kept on the side now. llvm-svn: 158867
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- Jun 02, 2012
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Jakob Stoklund Olesen authored
No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
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- Mar 04, 2012
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Craig Topper authored
llvm-svn: 152001
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- Feb 15, 2012
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Jakob Stoklund Olesen authored
Pretend that regmask interference ends at the 'dead' slot, even when there is other interference ending at the 'reg' slot of the same instruction. llvm-svn: 150531
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- Feb 10, 2012
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Jakob Stoklund Olesen authored
It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. llvm-svn: 150261
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Jakob Stoklund Olesen authored
This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. llvm-svn: 150259
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- Jan 13, 2012
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Andrew Trick authored
llvm-svn: 148143
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Andrew Trick authored
llvm-svn: 148103
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- Jul 23, 2011
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Jakob Stoklund Olesen authored
They always report 'no interference'. llvm-svn: 135843
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- Jul 14, 2011
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Jakob Stoklund Olesen authored
Original commit message: Count references to interference cache entries. Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135130
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Jakob Stoklund Olesen authored
llvm-svn: 135122
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Jakob Stoklund Olesen authored
Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135121
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- Apr 09, 2011
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Jakob Stoklund Olesen authored
This doesn't require seeking in the live interval union, so it is very cheap. llvm-svn: 129187
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- Apr 07, 2011
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Jakob Stoklund Olesen authored
llvm-svn: 129081
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- Apr 02, 2011
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Jakob Stoklund Olesen authored
When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. llvm-svn: 128764
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