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  1. Feb 21, 2013
  2. Feb 20, 2013
  3. Feb 12, 2013
  4. Feb 11, 2013
  5. Feb 10, 2013
  6. Jan 02, 2013
    • Chandler Carruth's avatar
      Move all of the header files which are involved in modelling the LLVM IR · 9fb823bb
      Chandler Carruth authored
      into their new header subdirectory: include/llvm/IR. This matches the
      directory structure of lib, and begins to correct a long standing point
      of file layout clutter in LLVM.
      
      There are still more header files to move here, but I wanted to handle
      them in separate commits to make tracking what files make sense at each
      layer easier.
      
      The only really questionable files here are the target intrinsic
      tablegen files. But that's a battle I'd rather not fight today.
      
      I've updated both CMake and Makefile build systems (I think, and my
      tests think, but I may have missed something).
      
      I've also re-sorted the includes throughout the project. I'll be
      committing updates to Clang, DragonEgg, and Polly momentarily.
      
      llvm-svn: 171366
      9fb823bb
  7. Dec 03, 2012
    • Chandler Carruth's avatar
      Use the new script to sort the includes of every file under lib. · ed0881b2
      Chandler Carruth authored
      Sooooo many of these had incorrect or strange main module includes.
      I have manually inspected all of these, and fixed the main module
      include to be the nearest plausible thing I could find. If you own or
      care about any of these source files, I encourage you to take some time
      and check that these edits were sensible. I can't have broken anything
      (I strictly added headers, and reordered them, never removed), but they
      may not be the headers you'd really like to identify as containing the
      API being implemented.
      
      Many forward declarations and missing includes were added to a header
      files to allow them to parse cleanly when included first. The main
      module rule does in fact have its merits. =]
      
      llvm-svn: 169131
      ed0881b2
  8. Jul 20, 2012
    • Jakob Stoklund Olesen's avatar
      Split loop exiting edges more aggressively. · f62c07f1
      Jakob Stoklund Olesen authored
      PHIElimination splits critical edges when it predicts it can resolve
      interference and eliminate copies. It doesn't split the edge if the
      interference wouldn't be resolved anyway because the phi-use register is
      live in the critical edge anyway.
      
      Teach PHIElimination to split loop exiting edges with interference, even
      if it wouldn't resolve the interference. This removes the necessary
      copies from the loop, which is still an improvement from injecting the
      copies into the loop.
      
      The test case demonstrates the improvement. Before:
      
      LBB0_1:
        cmpb  $0, (%rdx)
        leaq  1(%rdx), %rdx
        movl  %esi, %eax
        je  LBB0_1
      
      After:
      
      LBB0_1:
        cmpb  $0, (%rdx)
        leaq  1(%rdx), %rdx
        je  LBB0_1
      
        movl  %esi, %eax
      
      llvm-svn: 160571
      f62c07f1
  9. Jul 04, 2012
  10. Jun 25, 2012
    • Jakob Stoklund Olesen's avatar
      Teach PHIElimination to handle <undef> operands. · 70ed924e
      Jakob Stoklund Olesen authored
      When a PHI use is <undef>, don't emit a copy in the predecessor block,
      but insert an IMPLICIT_DEF instruction instead. This ensures that
      virtual register uses are always jointly dominated by defs, even if some
      of them are IMPLICIT_DEF.
      
      llvm-svn: 159121
      70ed924e
  11. Feb 10, 2012
    • Andrew Trick's avatar
      RegAlloc superpass: includes phi elimination, coalescing, and scheduling. · d3f8fe81
      Andrew Trick authored
      Creates a configurable regalloc pipeline.
      
      Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
      
      When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
      
      CodeGen transformation passes are never "required" as an analysis
      
      ProcessImplicitDefs does not require LiveVariables.
      
      We have a plan to massively simplify some of the early passes within the regalloc superpass.
      
      llvm-svn: 150226
      d3f8fe81
  12. Jan 20, 2012
  13. Dec 06, 2011
    • Evan Cheng's avatar
      First chunk of MachineInstr bundle support. · 2a81dd4a
      Evan Cheng authored
      1. Added opcode BUNDLE
      2. Taught MachineInstr class to deal with bundled MIs
      3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
      4. Taught MachineBasicBlock methods about bundled MIs
      
      llvm-svn: 145975
      2a81dd4a
  14. Jul 30, 2011
    • Jakob Stoklund Olesen's avatar
      Add an isSSA() flag to MachineRegisterInfo. · 9760f04e
      Jakob Stoklund Olesen authored
      This flag is true from isel to register allocation when the machine
      function is required to be in SSA form.  The TwoAddressInstructionPass
      and PHIElimination passes clear the flag.
      
      The SSA flag wil be used by the machine code verifier to check for SSA
      form, and eventually an assertion can enforce it in +Asserts builds.
      This will catch the common target error of creating machine code with
      multiple defs of a virtual register.
      
      llvm-svn: 136532
      9760f04e
  15. Apr 23, 2011
  16. Mar 10, 2011
  17. Feb 17, 2011
  18. Feb 14, 2011
  19. Jan 14, 2011
  20. Jan 13, 2011
  21. Jan 09, 2011
  22. Dec 05, 2010
  23. Dec 04, 2010
  24. Oct 08, 2010
  25. Aug 23, 2010
  26. Aug 18, 2010
  27. Aug 17, 2010
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