- Jul 14, 2011
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Evan Cheng authored
registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
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Chris Lattner authored
llvm-svn: 135183
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Chris Lattner authored
llvm-svn: 135182
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Eric Christopher authored
when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
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Jim Grosbach authored
Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
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Rafael Espindola authored
of named struct types. llvm-svn: 135178
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Chris Lattner authored
llvm-svn: 135174
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Chris Lattner authored
of calling getAllMetadata(). This is semantically identical, but doing it this way avoids unpacking the DebugLoc. llvm-svn: 135173
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Chris Lattner authored
an MDNode. This saves a bunch of time and memory in the IR linker, e.g. when doing LTO of files with debug info. llvm-svn: 135172
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Bruno Cardoso Lopes authored
llvm-svn: 135171
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Benjamin Kramer authored
llvm-svn: 135169
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Jim Grosbach authored
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
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Chris Lattner authored
llvm-svn: 135164
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Chris Lattner authored
non-virtual function. llvm-svn: 135163
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Chris Lattner authored
llvm-svn: 135157
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Jim Grosbach authored
The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
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Benjamin Kramer authored
llvm-svn: 135154
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Chris Lattner authored
llvm-svn: 135151
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Richard Osborne authored
instructions. llvm-svn: 135146
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Frits van Bommel authored
Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector. llvm-svn: 135145
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Nadav Rotem authored
[VECTOR-SELECT] During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
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Nadav Rotem authored
llvm-svn: 135143
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Chris Lattner authored
llvm-svn: 135132
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Evan Cheng authored
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are other cases of violations, but this is probably the worst. This patch is but one small step towards fixing this. 500 more steps to go. :-( llvm-svn: 135131
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Jakob Stoklund Olesen authored
Original commit message: Count references to interference cache entries. Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135130
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Devang Patel authored
llvm-svn: 135127
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Benjamin Kramer authored
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. llvm-svn: 135126
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Devang Patel authored
llvm-svn: 135124
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Eric Christopher authored
Fixes rdar://9761830 llvm-svn: 135123
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Jakob Stoklund Olesen authored
llvm-svn: 135122
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Jakob Stoklund Olesen authored
Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135121
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Eli Friedman authored
Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. llvm-svn: 135120
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Devang Patel authored
llvm-svn: 135118
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Jim Grosbach authored
Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
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Jakob Stoklund Olesen authored
The cache entry referenced by the best split candidate could become clobbered by an unsuccessful candidate. The correct fix here is to use reference counts on the cache entries. Coming up. llvm-svn: 135113
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Jim Grosbach authored
llvm-svn: 135112
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Devang Patel authored
llvm-svn: 135111
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Devang Patel authored
llvm-svn: 135110
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Jim Grosbach authored
Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
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Jim Grosbach authored
llvm-svn: 135107
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