- Nov 14, 2013
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Matt Arsenault authored
with the older version of the moveToVALU changes. llvm-svn: 194682
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Tom Stellard authored
Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
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Tom Stellard authored
All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
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- Nov 13, 2013
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Matt Arsenault authored
llvm-svn: 194547
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- Nov 12, 2013
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Matt Arsenault authored
Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
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Matt Arsenault authored
llvm-svn: 194433
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- Nov 11, 2013
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Vincent Lejeune authored
llvm-svn: 194425
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- Nov 06, 2013
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Vincent Lejeune authored
llvm-svn: 194153
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- Oct 31, 2013
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Matt Arsenault authored
llvm-svn: 193721
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- Oct 30, 2013
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Tom Stellard authored
llvm-svn: 193701
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- Oct 29, 2013
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Tom Stellard authored
v2: - Fix LDS size calculation Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
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Tom Stellard authored
llvm-svn: 193620
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- Oct 23, 2013
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Tom Stellard authored
This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 193222
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Tom Stellard authored
The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
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Tom Stellard authored
llvm-svn: 193213
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Tom Stellard authored
llvm-svn: 193212
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- Oct 22, 2013
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Tom Stellard authored
The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
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- Oct 21, 2013
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Matt Arsenault authored
llvm-svn: 193112
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Matt Arsenault authored
llvm-svn: 193111
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- Oct 16, 2013
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Tom Stellard authored
We were calling llvm_unreachable() when failing to optimize the branch into if case. However, it is still possible for us to structurize the CFG by duplicating blocks even if this optimization fails. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192813
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- Oct 13, 2013
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Vincent Lejeune authored
llvm-svn: 192557
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Vincent Lejeune authored
llvm-svn: 192554
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Vincent Lejeune authored
llvm-svn: 192553
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- Oct 11, 2013
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Matt Arsenault authored
llvm-svn: 192501
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Matt Arsenault authored
llvm-svn: 192500
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- Oct 10, 2013
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Matt Arsenault authored
llvm-svn: 192375
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Tom Stellard authored
We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
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- Oct 08, 2013
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Matt Arsenault authored
These are bugs to fix later. llvm-svn: 192212
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- Oct 01, 2013
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Vincent Lejeune authored
llvm-svn: 191790
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Vincent Lejeune authored
llvm-svn: 191789
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Vincent Lejeune authored
llvm-svn: 191788
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- Sep 30, 2013
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Manman Ren authored
llvm-svn: 191690
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Manman Ren authored
llvm-svn: 191689
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- Sep 28, 2013
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Tom Stellard authored
We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
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- Sep 13, 2013
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Vincent Lejeune authored
llvm-svn: 190644
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Vincent Lejeune authored
This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
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- Sep 12, 2013
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Tom Stellard authored
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
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- Sep 06, 2013
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Aaron Watry authored
Signed-off-by:
Aaron Watry <awatry@gmail.com> Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
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Matt Arsenault authored
llvm-svn: 190112
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- Sep 05, 2013
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Matt Arsenault authored
llvm-svn: 190091
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