Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

llvm-svn: 134569

llvm-svn: 134568

llvm-svn: 134566

When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors.  They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).

Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>

llvm-svn: 134565

llvm-svn: 134561

llvm-svn: 134559

llvm-svn: 134557

llvm-svn: 134555

llvm-svn: 134549

llvm-svn: 134547

llvm-svn: 134546

This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540

llvm-svn: 134538

careful about referencing values.

llvm-svn: 134537

Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533

llvm-svn: 134532

llvm-svn: 134530

llvm-svn: 134527

llvm-svn: 134525

llvm-svn: 134521

The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

llvm-svn: 134520

llvm-svn: 134516

push with a small constant produces a 2-byte push.

llvm-svn: 134501

llvm-svn: 134457

extension points to be used by clang.

llvm-svn: 134444

llvm-svn: 134441

llvm-svn: 134439

llvm-svn: 134436

llvm-svn: 134433

used for open is 0666.  Therefore, add the necessary permission bits for
consistency.
rdar://8621462

llvm-svn: 134430

This is impossible in theory, I can prove it. In practice, our near-zero
threshold can cause the network to oscillate between equally good
solutions.

<rdar://problem/9720596>

llvm-svn: 134428

llvm-svn: 134427

Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.

llvm-svn: 134424

Putting back the helper that I removed on 7/1 to do this right.

llvm-svn: 134423

If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415

Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

llvm-svn: 134413

llvm-svn: 134412

llvm-svn: 134408

PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use.

This can pessimize code, inequalities are generally more expensive.

llvm-svn: 134379

Noticed by Benjamin Kramer!

llvm-svn: 134376