llvm-svn: 77617

llvm-svn: 77616

llvm-svn: 77615

llvm-svn: 77614

llvm-svn: 77613

llvm-svn: 77612

llvm-svn: 77611

llvm-svn: 77610

current instantiation when that current instantiation is a class
template partial specialization.

llvm-svn: 77609

llvm-svn: 77608

llvm-svn: 77607

partial specializations.

llvm-svn: 77606

llvm-svn: 77605

llvm-svn: 77604

llvm-svn: 77603

llvm-svn: 77602

classes. And define its SubRegClassList.

llvm-svn: 77601

llvm-svn: 77599

llvm-svn: 77598

llvm-svn: 77597

llvm-svn: 77589

llvm-svn: 77587

Allow targets to define libcall names for mem(cpy,set,move) intrinsics, rather than hardcoding them in DAG lowering.

llvm-svn: 77586

Move all components creation code into AnalysisConsumer::DigestAnalyzerOptions().

llvm-svn: 77585

llvm-svn: 77584

I've changed the semantics of MERGE_VALUES a bit. It's now allowed to live until scheduling. It's deleted when the scheduler translate DAG nodes to machine instructions.

This is currently used by X86 to handle atomic_load_add when the output of the node is not used. I believe there is a better solution. But I find MERGE_VALUES useful for selecting multi-output node when the dead output can be selected as a IMPLICIT_DEF.

llvm-svn: 77583

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

a Twine, e.g., for names).
 - I am a little ambivalent about this; we don't want the string conversion of
   utostr, but using overload '+' mixed with string and integer arguments is
   sketchy. On the other hand, this particular usage is something of an idiom.

llvm-svn: 77579

declaration for them.

llvm-svn: 77578

llvm-svn: 77577

explicitly.

llvm-svn: 77576

llvm-svn: 77575

llvm-svn: 77573

llvm-svn: 77571

llvm-svn: 77570

llvm-svn: 77569

llvm-svn: 77568

value.

llvm-svn: 77566

due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565

llvm-svn: 77564