llvm-svn: 81987

llvm-svn: 81985

the same time.

llvm-svn: 81984

All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.

llvm-svn: 81979

llvm-svn: 81970

llvm-svn: 81969

llvm-svn: 81968

one implementation into its one caller.  This eliminates a totally
awesome and gratuitous hack where we casted a Function* to 
GlobalVariable*.

llvm-svn: 81967

llvm-svn: 81966

and use PersonalityPrefix/Suffix to achieve the same effect (like
the x86 backend).

This changes the code generated for ppc static mode, but guess what,
we were generating this before:

	.byte	0x9B                                        ; Personality (indirect pcrel sdata4)
	.long	___gxx_personality_v0-.                     ; Personality

which is not correct! (it is not an 'indirect' reference).
 

llvm-svn: 81965

it into all of its call sites and simplifying them.

llvm-svn: 81962

llvm-svn: 81961

Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)

llvm-svn: 81959

llvm-svn: 81954

code in other segments) to the Intel instruction
tables.

llvm-svn: 81953

llvm-svn: 81946

llvm-svn: 81942

move MachineFunctionInfo virtual method out of line to give it
a home.

llvm-svn: 81940

SVOffsets.

llvm-svn: 81937

llvm-svn: 81928

llvm-svn: 81923

llvm-svn: 81915

Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914

 - As best I can tell, we have eliminated all the code which used to require a
   larger buffer size.

llvm-svn: 81912

llvm-svn: 81911

llvm-svn: 81910

llvm-svn: 81909

is a site configuration.

llvm-svn: 81902

Better solution for tracking both the original alignment of the access, and the current alignment based
on the source value offset.  This avoids increasing the size of mem nodes. 

llvm-svn: 81897

llvm-svn: 81896

to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895

interrupt instruction, which shouldn't arise any other way).  0xcd is
also used by JITMemoryManager to initialize the buffer to garbage,
which means it could appear following a noreturn call even when
that is not a stub, confusing X86CompilationCallback2.  PR 4929.

llvm-svn: 81888

values to machineinstrs.

llvm-svn: 81886

llvm-svn: 81884

llvm-svn: 81882

llvm-svn: 81881

VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR.  The asm printer,
however, silently drops the offset, producing incorrect code.  Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.

llvm-svn: 81879

llvm-svn: 81878

and PIC codegen.  Patch by Venkatraman Govindaraju!

llvm-svn: 81877

not folded in the constant folder because the constant folder doesn't
simplify ConstantExpr operands.

llvm-svn: 81864