llvm-svn: 81726

llvm-svn: 81128

about by icc (#593, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81115

swapping the operands if necessary.

llvm-svn: 80940

  - when transforming a vector shift of a non-immediate scalar shift amount, zero
    extend the i32 shift amount to i64 since the vector shift reads 64 bits
  - when transforming i16 vectors to use a vector shift, zero extend i16 shift amount
  - improve the code quality in some cases when transforming vectors to use a vector shift

llvm-svn: 80935

disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.

llvm-svn: 80930

llvm-svn: 80773

llvm-svn: 80764

handling on x86-32 linux.

llvm-svn: 80592

  encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
  size. This is in line with how GCC does things. And it has the benefit of
  working for Darwin in 64-bit mode now.

llvm-svn: 80428

llvm-svn: 80269

llvm-svn: 80268

moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.

subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.

llvm-svn: 80184

llvm-svn: 79742

Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).

llvm-svn: 79377

returns a log2 value.

llvm-svn: 79293

or some other situation where no xmm registers need to be saved.

llvm-svn: 79207

llvm-svn: 79136

llvm-svn: 79135

support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127

the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.

llvm-svn: 79061

llvm-svn: 79009

llvm-svn: 78948

llvm-svn: 78725

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610

llvm-svn: 78595

llvm-svn: 78593

Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.

llvm-svn: 78584

subtle bug with small code model.

llvm-svn: 78255

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

llvm-svn: 77965

Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).

llvm-svn: 77964

Cleanup Darwin MMX calling conv stuff - make the stuff more generic. This also fixes a subtle bug, when 6th v1i64 argument passed wrongly.

llvm-svn: 77963

Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.

llvm-svn: 77962

Thanks to Eli Friedman for noticing it.

llvm-svn: 77942

Fixes PR4669

llvm-svn: 77940

llvm-svn: 77795

initialize method, which can be called when an MCContext is available.

llvm-svn: 77687

classes. And define its SubRegClassList.

llvm-svn: 77601