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  1. Mar 19, 2010
    • Chris Lattner's avatar
      comment out a bunch of parallel store patterns that apparently · 607795f9
      Chris Lattner authored
      can't match or just have no testcases.  Will remove after 
      confirmation from dan that they really are dead.
      
      llvm-svn: 98930
      607795f9
    • Daniel Dunbar's avatar
      X86: Fix encoding for TEST64rr. · c9deca20
      Daniel Dunbar authored
      llvm-svn: 98919
      c9deca20
    • Chris Lattner's avatar
      Now that tblgen can handle matching implicit defs of instructions · 83facb08
      Chris Lattner authored
      to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
      two inputs (which have to be the same type) and *returning an i32*.
      This is how the SDNodes get made in the graph, but we weren't able
      to model it this way due to deficiencies in the pattern language.
      
      Now we can change things like this:
      
       def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
      -                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
      -                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
      +                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
      
      and fix terrible crimes like this:
      
      -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
      +def : Pat<(X86cmp GR8:$src1, 0),
                 (TEST8rr GR8:$src1, GR8:$src1)>;
      
      This relies on matching the result of TEST8rr (which is EFLAGS, which is
      an implicit def) to the result of X86cmp, an i32.
      
      llvm-svn: 98903
      83facb08
  2. Mar 18, 2010
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