llvm-svn: 64040

No functional change.

llvm-svn: 64026

ScheduleDAG's TLI member to use const.

llvm-svn: 64018

Adjust derived classes to pass UnknownLoc where
a DebugLoc does not make sense.  Pick one of
DebugLoc and non-DebugLoc variants to survive
for all such classes.

llvm-svn: 64000

llvm-svn: 63999

llvm-svn: 63995

Don't sink the instruction if TargetRegisterInfo::isSafeToMoveRegClassDefs doesn't think it's safe. This works around PR1911.

llvm-svn: 63994

Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.

llvm-svn: 63992

getCALLSEQ_{END,START} to permit passing no DebugLoc
there.  UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.

llvm-svn: 63978

llvm-svn: 63971

llvm-svn: 63969

llvm-svn: 63967

llvm-svn: 63951

SelectionDAGISel::CreateScheduler, and make it just create the
scheduler. Leave running the scheduler to the higher-level code.
This makes the higher-level code a little more explicit and
easier to follow, and will help enable some future refactoring.

llvm-svn: 63944

llvm-svn: 63941

llvm-svn: 63938

that previously included this header should include
SchedulerRegistry.h instead.

llvm-svn: 63937

Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.

llvm-svn: 63936

that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).

llvm-svn: 63934

llvm-svn: 63909

its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904

isAsCheapAsMove instructions can have register src operands. Check if they are really re-materializable.
This fixes sse.expandfft and sse.stepfft.

llvm-svn: 63890

llvm-svn: 63889

llvm-svn: 63886

Machine LICM increases register pressure and it almost always increase code size. For now, disable it for optimizing for size.

llvm-svn: 63856

llvm-svn: 63855

llvm-svn: 63854

ReMaterializeTrivialDef need to trim the live interval to the last kill if the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove.

llvm-svn: 63853

sure to print the value properly sext'd to the right pointer size.
This fixes PR3481.

llvm-svn: 63843

between call frame setup/restore points.  Unfortunately, this regresses 
code size a bit, but at least it's correct now!

llvm-svn: 63837

between a unsigned integer and signed integer.

llvm-svn: 63831

llvm-svn: 63812

llvm-svn: 63808

llvm-svn: 63800

Adjust callers.

llvm-svn: 63789

and llvm-gcc.

llvm-svn: 63786

llvm-svn: 63768

Adjust the many callers of those versions.

llvm-svn: 63767

target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.

llvm-svn: 63765

but when legalizing the operation, we split the vector type and generate a library
call whose type needs to be promoted. For example, X86 with SSE on but MMX off, 
a divide v2i64 will be scalarized to 2 calls to a library using i64.

llvm-svn: 63760