llvm-svn: 173513

The test runner does not rewrite instances of /dev/null inside the
quoted sh command.  /dev/null does not exist, so opt will fail to open
it, and return a non-zero exit code.

llvm-svn: 173509

Cygwin git-svn will faithfully forward the svn properties all the way
down to the NTFS executable permission.  Without the +x bit, tests using
these scripts fail with "Access Denied".

llvm-svn: 173508

It doesn't seem to like instantiating the isUInt<unsigned N> template
with 6+3, and then doing <<N.

llvm-svn: 173507

These tests in particular try to use escaped square brackets as an
argument to grep, which is failing for me with native win32 python.  It
appears the backslash is being lost near the CreateProcess*() call.

llvm-svn: 173506

llvm-svn: 173505

(defined by the x32 ABI) mode, in which case its pointers are 32-bits
in size. This knowledge is also added to X86RegisterInfo that now
returns the appropriate registers in getPointerRegClass.

There are many outcomes to this change. In order to keep the patches
separate and manageable, we start by focusing on some simple testable
cases. The patch adds a test with passing a pointer to a function -
focusing on the difference between the two data models for x86-64.
Another test is added for handling of 'sret' arguments (and
functionality is added in X86ISelLowering to make it work).

A note on naming: the "x32 ABI" document refers to the AMD64
architecture (in LLVM it's distinguished by being is64Bits() in the
x86 subtarget) with two variations: the LP64 (default) data model, and
the ILP32 data model. This patch adds predicates to the subtarget
which are consistent with this naming scheme.

llvm-svn: 173503

llvm-svn: 173502

llvm-svn: 173501

llvm-svn: 173500

llvm-svn: 173499

use them in tests that run llvm-dwarfdump. This is in order to make tests as
specific as possible.

llvm-svn: 173498

llvm-svn: 173497

llvm-svn: 173495

llvm-svn: 173494

The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

llvm-svn: 173493

politely report it instead of running into llvm_unreachable.

Also patch llvm-dwarfdump to actually check whether the file it's attempting to
dump is a valid object file.

llvm-svn: 173489

llvm-svn: 173487

Suggested by Sean Silva.

llvm-svn: 173481

Flags for dumping specific DWARF sections added in lib/DebugInfo and
llvm-dwarfdump.

llvm-svn: 173480

llvm-svn: 173479

llvm-svn: 173478

With this change the operands order matches the order in which the operands
are encoded in the instruction.

llvm-svn: 173477

llvm-svn: 173476

llvm-svn: 173475

created InternalizePass (useful for pass reuse)

llvm-svn: 173474

custom git script called git-svnup which handles all of the work of
using the git-mirrors/keeping the git-svn numbers in sync.

llvm-svn: 173472

llvm-svn: 173471

llvm-svn: 173468

llvm-svn: 173467

llvm-svn: 173460

Fixes PR15054.

llvm-svn: 173459

This warning fires on:
  Operator::~Operator() {
    llvm_unreachable("should never destroy an Operator");
  }

That seems like a false positive.  I don't see any good way to silence
the warning here, so I'm disabling it.

llvm-svn: 173455

llvm-svn: 173454

llvm-svn: 173453

Only for integers, pointers, and vectors of those. No floats.
Instrumentation seems very heavy, and may need to be replaced
with some approximation in the future.

llvm-svn: 173452

with an initial number of elements,  instead of DenseMap, which has
zero initial elements, in order to avoid the copying of elements
when the size changes and to avoid allocating space every time
LegalizeTypes is run. This patch will not affect the memory footprint,
because DenseMap will increase the element size to 64
when the first element is added.

Patch by Wan Xiaofei.

llvm-svn: 173448

Uses the new !add TableGen operator to do more cleanup of the
PPC register definitions.

llvm-svn: 173446

This adds an !add(a, b) operator to tablegen; this will be used
to cleanup the PPC register definitions.

llvm-svn: 173445

Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.

llvm-svn: 173437