llvm-svn: 60039

(a) Remove conditionally removed code in SelectXAddr. Basically, hope for the
    best that the A-form and D-form address predicates catch everything before
    the code decides to emit a X-form address.
(b) Expand vector store test cases to include the usual suspects.

llvm-svn: 60034

llvm-svn: 60030

llvm-svn: 60016

llvm-svn: 60015

if the operands have the same sign and the sum has sign opposite to that of the
operands."

llvm-svn: 60014

can recursively match things) and scales by 0 by ignoring them.
This triggers once in 403.gcc, saving 1 (!!!!) instruction in the 
whole huge app.

llvm-svn: 60013

into a new AddressingModeMatcher class.  This makes it easier
to reason about and reduces passing around of stuff, but has
no functionality change.

llvm-svn: 60012

new FindMaximalLegalAddressingModeForOperation helper method.

llvm-svn: 60011

llvm-svn: 60010

llvm-svn: 60009

llvm-svn: 60008

they were too tight according to bug 3126.

Fix bug 3126.

llvm-svn: 60006

llvm-svn: 60001

llvm-svn: 60000

introduce any new spilling; it just uses unused registers.

Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.

llvm-svn: 59999

llvm-svn: 59998

llvm-svn: 59992

llvm-svn: 59990

llvm-svn: 59989

llvm-svn: 59986

llvm-svn: 59985

llvm-svn: 59981

simplify header dependencies for front-ends that just want to choose
a scheduler and don't need all the scheduling machinery declarations.

llvm-svn: 59978

llvm-svn: 59977

llvm-svn: 59976

with an undef.

llvm-svn: 59972

- Mark "add with overflow" as having a custom lowering for X86. Give it a null
  lowering representation for now.

llvm-svn: 59971

(a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to
    directly zero-extend i32 to i64, but use rotates and shifts for
    sign extension. Also ensure unified register consistency.
(b) Add new test harness for i64 operations: i64ops.ll

llvm-svn: 59970

to removePred because an SUnit can both data-depend and anti-depend
on the same SUnit.

llvm-svn: 59969

llvm-svn: 59968

obscure tail-merging opportunities.

llvm-svn: 59967

llvm-svn: 59966

(a) Improve the extract element code: there's no need to do gymnastics with
    rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
    semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.

llvm-svn: 59965

llvm-svn: 59964

llvm-svn: 59963

llvm-svn: 59962

llvm-svn: 59961

(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types.  I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.

llvm-svn: 59960

llvm-svn: 59958