us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register.  This also requires some asm printer work
to satisfy the darwin assembler.

For
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

We now produce:
_foo:
        lvx v0, 0, r3
        vaddfp v0, v0, v0
        stvx v0, 0, r3
        blr

Instead of:
_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24872

llvm-svn: 24871

llvm-svn: 24870

llvm-svn: 24869

llvm-svn: 24867

creating graphs that cannot be scheduled.

llvm-svn: 24866

Make the dsa-alloc-list and dsa-free-list options hidden.

llvm-svn: 24864

llvm-svn: 24863

functions that allocate memory.

llvm-svn: 24862

llvm-svn: 24861

latency period between the two.

llvm-svn: 24860

we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.

llvm-svn: 24859

llvm-svn: 24857

llvm-svn: 24856

llvm-svn: 24855

llvm-svn: 24854

llvm-svn: 24853

llvm-svn: 24852

llvm-svn: 24850

llvm-svn: 24849

llvm-svn: 24848

llvm-svn: 24847

llvm-svn: 24846

llvm-svn: 24845

llvm-svn: 24844

llvm-svn: 24843

llvm-svn: 24842

llvm-svn: 24841

llvm-svn: 24840

llvm-svn: 24839

llvm-svn: 24838

llvm-svn: 24837

llvm-svn: 24836

llvm-svn: 24835

llvm-svn: 24834

llvm-svn: 24832

a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.

llvm-svn: 24830

llvm-svn: 24828

llvm-svn: 24826

llvm-svn: 24825