MSVC 2012 gives warning D9025, "overriding /D NDEBUG with -UNDEBUG".
Removing the original definition of NDEBUG silences this.

llvm-svn: 178967

Integer return values are sign or zero extended by the callee, and
structs up to 32 bytes in size can be returned in registers.

The CC_Sparc64 CallingConv definition is shared between
LowerFormalArguments_64 and LowerReturn_64. Function arguments and
return values are passed in the same registers.

The inreg flag is also used for return values. This is required to handle
C functions returning structs containing floats and ints:

  struct ifp {
    int i;
    float f;
  };

  struct ifp f(void);

LLVM IR:

  define inreg { i32, float } @f() {
     ...
     ret { i32, float } %retval
  }

The ABI requires that %retval.i is returned in the high bits of %i0
while %retval.f goes in %f1.

Without the inreg return value attribute, %retval.i would go in %i0 and
%retval.f would go in %f3 which is a more efficient way of returning
%multiple values, but it is not ABI compliant for returning C structs.

llvm-svn: 178966

64-bit SPARC v9 processes use biased stack and frame pointers, so the
current function's stack frame is located at %sp+BIAS .. %fp+BIAS where
BIAS = 2047.

This makes more local variables directly accessible via [%fp+simm13]
addressing.

llvm-svn: 178965

re-fetch the value.

llvm-svn: 178962

There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).

llvm-svn: 178961

llvm-svn: 178960

This comment documents the current behavior of the ARM implementation of this
callback, and also the soon-to-be-committed PPC version.

llvm-svn: 178959

All arguments are formally assigned to stack positions and then promoted
to floating point and integer registers. Since there are more floating
point registers than integer registers, this can cause situations where
floating point arguments are assigned to registers after integer
arguments that where assigned to the stack.

Use the inreg flag to indicate 32-bit fragments of structs containing
both float and int members.

The three-way shadowing between stack, integer, and floating point
registers requires custom argument lowering. The good news is that
return values are passed in the exact same way, and we can share the
code.

Still missing:

 - Update LowerReturn to handle structs returned in registers.
 - LowerCall.
 - Variadic functions.

llvm-svn: 178958

llvm-svn: 178955

llvm-svn: 178954

if we have an updated task_info call available; else fall back to getting
the default host-wide page size.

Update all uses of the vm page size to get it via MachVMMemory::PageSize().

<rdar://problem/13477763>, <rdar://problem/13498504> 

llvm-svn: 178953

llvm-svn: 178952

to 'off' for a week or so while we test the behavior in different environments.

llvm-svn: 178951

linkage specification, and is marked as __attribute__((used)), try to also give
it the unmangled name (by emitting an internal linkage alias) if nothing else
within the translation unit would use that name. This allows inline asm in that
translation unit to use the entity via its unmangled name, which people
apparently rely on.

llvm-svn: 178950

llvm-svn: 178949

llvm-svn: 178948

This also required not using the RegisterStringTable API, which is also a
good thing.

llvm-svn: 178947

llvm-svn: 178946

llvm-svn: 178945

This is important because sometimes two nodes are identical, except the
second one is a sink.

This bug has probably been around for a while, but it wouldn't have been an
issue in the old report graph algorithm. I'm ashamed to say I actually looked
at this the first time around and thought it would never be a problem...and
then didn't include an assertion to back that up.

PR15684

llvm-svn: 178944

llvm-svn: 178943

rdar://13181413

llvm-svn: 178942

We used to do "SmallString += CUID", which is incorrect, since CUID will
be truncated to a char.

rdar://problem/13573833

llvm-svn: 178941

llvm-svn: 178940

<rdar://problem/13325066> Destroy std::initializer_list temporaries whose lifetime has been extended by reference binding.

llvm-svn: 178939

As per Ted’s suggestion!

llvm-svn: 178938

New rule:
- Method decls in @implementation are considered "redeclarations"
  and inherit deprecated/availability from the @interface.
- All other cases are consider overrides, which do not inherit
  deprecated/availability.  For example:

  (a) @interface redeclares a method in an adopted protocol.
  (b) A subclass redeclares a method in a superclass.
  (c) A protocol redeclares a method from another protocol it adopts.

The idea is that API authors should have the ability to easily
move availability/deprecated up and down a class/protocol hierarchy.
A redeclaration means that the availability/deprecation is a blank
slate.

Fixes <rdar://problem/13574571>

llvm-svn: 178937

Don't call DisableBreakpointSite (i.e. don't try to remove the breakpoint from the target process) if the target
process is no longer alive.

<rdar://problem/13320991>

llvm-svn: 178936

llvm-svn: 178935

llvm-svn: 178934

[analyzer] Fix null tracking for the given test case, by using the proper state and removing redundant code.

llvm-svn: 178933

llvm-svn: 178932

v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931

The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930

This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928

SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927

On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.

Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.

llvm-svn: 178926

The manual states that there is a minimum of 13 cycles from when the
mispredicted branch is issued to when the correct branch target is
issued.

llvm-svn: 178925

Now we can:
1 - see the return value for functions that return types that use the "ext_vector_size"
2 - dump values that use the vector attributes ("expr $ymm0")
3 - modified the DWARF parser to correctly parse GNU vector types from the DWARF by turning them into clang::Type::ExtVector types instead of just standard arrays

llvm-svn: 178924