llvm-svn: 41595

Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.

llvm-svn: 41587

in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.

llvm-svn: 41577

llvm-svn: 41502

Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479

changing the interface to allow for future changes.

llvm-svn: 41384

llvm-svn: 41359

llvm-svn: 41319

llvm-svn: 41284

llvm-svn: 41208

 *) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179

llvm-svn: 41178

hard to catch bugs with retaddr lowering

llvm-svn: 41104

llvm-svn: 41103

llvm-svn: 41059

see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049

llvm-svn: 41048

llvm-svn: 41021

able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020

Make a 'memop' pattern just for them.

llvm-svn: 41017

llvm-svn: 41013

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

llvm-svn: 41009

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40986

llvm-svn: 40985

llvm-svn: 40982

llvm-svn: 40973

divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.

llvm-svn: 40972

GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.

llvm-svn: 40970

(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958

SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906

Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886

llvm-svn: 40881

llvm-svn: 40878

(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877

llvm-svn: 40868

Lots of problems yet but some simple things work.

llvm-svn: 40847

This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.

This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807

Darwin (which makes size within a struct==96)

llvm-svn: 40796