llvm-svn: 27227

llvm-svn: 27225

llvm-svn: 27223

llvm-svn: 27222

llvm-svn: 27221

llvm-svn: 27220

llvm-svn: 27219

* Bug fixes.

llvm-svn: 27218

llvm-svn: 27216

llvm-svn: 27215

llvm-svn: 27212

llvm-svn: 27211

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

llvm-svn: 27209

same thing and we have a dag node for the former.

llvm-svn: 27205

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.

llvm-svn: 27201

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27180

llvm-svn: 27174

llvm-svn: 27170

llvm-svn: 27168

llvm-svn: 27167

llvm-svn: 27166

llvm-svn: 27160

llvm-svn: 27159

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27153

llvm-svn: 27152

llvm-svn: 27151

llvm-svn: 27150

llvm-svn: 27149

llvm-svn: 27148

non-predicate altivec compare intrinsics.

llvm-svn: 27143

intrinsics.

llvm-svn: 27142

llvm-svn: 27139

llvm-svn: 27136

CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC

llvm-svn: 27135

llvm-svn: 27132

llvm-svn: 27127

llvm-svn: 27120