- Oct 15, 2012
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Jakob Stoklund Olesen authored
Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
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Jakob Stoklund Olesen authored
Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
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Jim Grosbach authored
rdar://12502028 llvm-svn: 165981
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Bill Wendling authored
Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change. llvm-svn: 165960
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Chad Rosier authored
llvm-svn: 165955
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Rafael Espindola authored
follow in one sec. llvm-svn: 165951
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Andrew Trick authored
llvm-svn: 165950
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Chad Rosier authored
llvm-svn: 165947
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Chad Rosier authored
inline assembly. For the time being, these will be called directly by clang. However, in the near future I expect these to be sunk back into the MC layer and more basic APIs (e.g., getClobbers(), getConstraints(), etc.) will be called by clang. llvm-svn: 165946
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Chad Rosier authored
llvm-svn: 165945
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Micah Villmow authored
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis. llvm-svn: 165941
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Adhemerval Zanella authored
This patch replaces the EmitRawText by a EmitTCEntry class (specialized for each Streamer) in PowerPC64 TOC entry creation. llvm-svn: 165940
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Kostya Serebryany authored
[asan] make AddressSanitizer to be a FunctionPass instead of ModulePass. This will simplify chaining other FunctionPasses with asan. Also some minor cleanup llvm-svn: 165936
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Chandler Carruth authored
includes extracting ints for copying elsewhere and inserting ints when copying into the alloca. This should fix the CanSROA assertion coming out of Clang's regression test suite. llvm-svn: 165931
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Chandler Carruth authored
and generally clean up the memset handling. It had rotted a bit as the other rewriting logic got polished more. llvm-svn: 165930
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Silviu Baranga authored
Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE. llvm-svn: 165929
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Chandler Carruth authored
cases where we have partial integer loads and stores to an otherwise promotable alloca to widen[1] those loads and stores to cover the entire alloca and bitcast them into the appropriate type such that promotion can proceed. These partial loads and stores stem from an annoying confluence of ARM's calling convention and ABI lowering and the FCA pre-splitting which takes place in SROA. Clang lowers a { double, double } in-register function argument as a [4 x i32] function argument to ensure it is placed into integer 32-bit registers (a really unnerving implicit contract between Clang and the ARM backend I would add). This results in a FCA load of [4 x i32]* from the { double, double } alloca, and SROA decomposes this into a sequence of i32 loads and stores. Inlining proceeds, code gets folded, but at the end of the day, we still have i32 stores to the low and high halves of a double alloca. Widening these to be i64 operations, and bitcasting them to double prior to loading or storing allows promotion to proceed for these allocas. I looked quite a bit changing the IR which Clang produces for this case to be more friendly, but small changes seem unlikely to help. I think the best representation we could use currently would be to pass 4 i32 arguments thereby avoiding any FCAs, but that would still require this fix. It seems like it might eventually be nice to somehow encode the ABI register selection choices outside of the parameter type system so that the parameter can be a { double, double }, but the CC register annotations indicate that this should be passed via 4 integer registers. This patch does not address the second problem in PR14059, which is the reverse: when a struct alloca is loaded as a *larger* single integer. This patch also does not address some of the code quality issues with the FCA-splitting. Those don't actually impede any optimizations really, but they're on my list to clean up. [1]: Pedantic footnote: for those concerned about memory model issues here, this is safe. For the alloca to be promotable, it cannot escape or have any use of its address that could allow these loads or stores to be racing. Thus, widening is always safe. llvm-svn: 165928
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Chandler Carruth authored
into static helper functions. They're really quite generic and are going to be needed elsewhere shortly. llvm-svn: 165927
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Bill Wendling authored
Add an enum for the return and function indexes into the AttrListPtr object. This gets rid of some magic numbers. llvm-svn: 165924
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Bill Wendling authored
llvm-svn: 165923
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Bill Wendling authored
llvm-svn: 165920
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Bill Wendling authored
Convert the internal representation of the Attributes class into a pointer to an opaque object that's uniqued by and stored in the LLVMContext object. The Attributes class then becomes a thin wrapper around this opaque object. Eventually, the internal representation will be expanded to include attributes that represent code generation options, etc. llvm-svn: 165917
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Meador Inge authored
This patch migrates the strcmp and strncmp optimizations from the simplify-libcalls pass into the instcombine library call simplifier. llvm-svn: 165915
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- Oct 14, 2012
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Benjamin Kramer authored
llvm-svn: 165904
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Benjamin Kramer authored
Erasing from the beginning or middle of the vector is expensive, remove_if can do it in linear time even though it's a bit ugly without lambdas. No functionality change. llvm-svn: 165903
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Bill Wendling authored
llvm-svn: 165902
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Bill Wendling authored
llvm-svn: 165899
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Benjamin Kramer authored
Can't follow the intrusive linked list when the element is gone. llvm-svn: 165898
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Bill Wendling authored
llvm-svn: 165897
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Bill Wendling authored
Remove the bitwise AND operators from the Attributes class. Replace it with the equivalent from the builder class. llvm-svn: 165896
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Bill Wendling authored
Remove the bitwise assignment OR operator from the Attributes class. Replace it with the equivalent from the builder class. llvm-svn: 165895
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Bill Wendling authored
Remove the bitwise OR operator from the Attributes class. Replace it with the equivalent from the builder class. llvm-svn: 165894
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Bill Wendling authored
Remove the bitwise XOR operator from the Attributes class. Replace it with the equivalent from the builder class. llvm-svn: 165893
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Bill Wendling authored
Remove the bitwise NOT operator from the Attributes class. Replace it with the equivalent from the builder class. llvm-svn: 165892
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Bill Wendling authored
llvm-svn: 165891
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Bill Wendling authored
llvm-svn: 165890
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Bill Wendling authored
llvm-svn: 165887
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- Oct 13, 2012
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Benjamin Kramer authored
llvm-svn: 165881
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Benjamin Kramer authored
llvm-svn: 165878
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Jakob Stoklund Olesen authored
The new coalescer can merge a dead def into an unused lane of an otherwise live vector register. Clear the <dead> flag when that happens since the flag refers to the full virtual register which is still live after the partial dead def. This fixes PR14079. llvm-svn: 165877
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